University of Central Florida STARS Electronic Theses and Dissertations, 2004-2019 2007 Gate Stack And Channel Engineering: Study Of Metal Gates And Ge Channel Devices Ravi Todi University of Central Florida Part of the Electrical and Electronics Commons Find similar works at: https://stars.library.ucf.edu/etd University of Central Florida Libraries http://library.ucf.edu This Doctoral Dissertation (Open Access) is brought to you for free and open access by STARS. It has been accepted for inclusion in Electronic Theses and Dissertations, 2004-2019 by an authorized administrator of STARS. For more information, please contact [email protected]. STARS Citation Todi, Ravi, "Gate Stack And Channel Engineering: Study Of Metal Gates And Ge Channel Devices" (2007). Electronic Theses and Dissertations, 2004-2019. 3387. https://stars.library.ucf.edu/etd/3387 GATE STACK AND CHANNEL ENGINEERING: STUDY OF METAL GATES AND Ge CHANNEL DEVICES by RAVI M. TODI B.E.E.E. Mumbai University, 2002 M.S.E.E., University of Central Florida, 2004 M.S.M.E., University of Central Florida, 2005 A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the School of Electrical Engineering and Computer Science in the College of Engineering and Computer Science at the University of Central Florida Orlando, Florida Spring Term 2007 Major Professors: Kevin R. Coffey Kalpathy B. Sundaram © 2007 Ravi M. Todi ii ABSTRACT The continued scaling of device dimensions in complementary metal oxide semiconductor (CMOS) technology within the sub-100 nm region requires an alternative high dielectric constant (high-κ) oxide layer to counter high tunneling leakage currents, a metallic gate electrode to address polysilicon depletion, boron penetration and high polysilicon sheet resistance, and high mobility channel materials to boost the CMOS performance. Metal gates can also offer improved thermal and chemical stability, but their use requires that we improve our understanding of how the metal alloy phase, crystallographic orientation, and composition affect the electronic properties of the metal alloy-oxide interface. To replace n++ and p++ polysilicon gate electrodes and maintain scaled device performance requires metal gate electrodes with work functions within 0.2 eV of the silicon conduction and valence band edges, i.e., 5.0-5.2 and 4.1-4.3 eV, for PMOS and NMOS devices, respectively. In addition to work function and thermal/chemical stability, metal gates must be integrated into the CMOS process flow. It is the aim of this work to significantly expand our knowledge base in alloys for dual metal gates by carrying out detailed electrical and materials studies of the binary alloy systems of Ru with p-type metal Pt. Three n-type metals systems, Ru-Ta, Ru-Hf and Ru-Nb have also been partially investigated. This work also focuses on high mobility Ge p-MOSFETs for improved CMOS performance. DC magnetron sputtering has been used to deposit binary alloy films on thermally grown SiO2. The composition of the alloy films have been determined by Rutherford backscattering spectrometry and the identification of phases present have been made using x-ray and electron diffraction of samples. The microstructure of the phases of interest has been examined in the iii transmission electron microscope and film texture was characterized via x-ray diffraction. The electrical characterization includes basic resistivity measurements, and work function extraction. The work function has been determined from MOS capacitor and Schottky diodes. The need for electron and hole mobility enhancement and the progress in the development of high-κ gate stacks, has lead to renewed interest in Ge MOSFETs. The p-MOS mobility data for Ge channel devices have been reported. The results indicate greater than 2 x improvements in device mobility as compared to standard Si device. A low frequency noise assessment of silicon passivated Ge p-MOSFETs with a TiN/TaN/HfO2 gate stack has been made. For the first time we also report results on low frequency noise characterisation for a Ge P+- n junctions with and without Ni germanidation. iv dedicated to my grandparents and parents Shri Ramlal Todi & Late Smt. Mohini Devi Todi Shri Mahendra Kumar Todi and Smt. Kusum M. Todi who have always been inspirational sources in helping me realize my goals v ACKNOWLEDGMENTS First and foremost, I would like to acknowledge and thank my advisors Dr. Kalpathy B. Sundaram and Kevin R. Coffey for their guidance and support which was crucial for the completion of this work. Thanks to Prof. John Shen and Prof. J. S. Yuan for serving on my dissertation committee and for their valuable advice and comments that helped me improve the quality of my dissertation. I would like to acknowledge Prof. Katayun Barmak from Department of Materials Science and Engineering at Carnegie Mellon University for valuable discussions from time to time. Special acknowledgement is due to my promoter at K. U. Leuven Prof. Cor Claeys, for facilitating my summer internship at IMEC. I also thank Ge III-V program manager Dr. Marc Meuris for his support and guidance during my stay at IMEC. I am grateful to Edward Dein and Kevin Casey for giving me my first lessons in the cleanroom and for helpful suggestions at all times. I also wish to acknowledge advanced microfabrication facility (AMF) and the materials characterization facility (MCF) at the advanced materials processing and analysis center (AMPAC) for laboratory support at the University of Central Florida (UCF). I gratefully acknowledge the faculty and staff at AMPAC, the School of Electrical Engineering and Computer Science and the College of Engineering and Computer Science at UCF for academic support for nearly five years. I would like to thank my current and former colleagues at UCF; Mr. Arun Vijayakumar, Mr. Sumant Sood, Mr. Parag Gadkari, Mr. Andrew Warren, Dr. Rumyana Petrova, Mr. Vu Lam, Ms. Chaitali China, Mr. Bo Yao and Vinit Todi, who helped me tremendously throughout all the experiments. I would also like to acknowledge my colleagues at IMEC; Dr. Gareth Nicholas, Mr. Jan Van Steenbergen, Mr. Brice De Jaeger, Dr. Paul Zimmerman and Mr. Sushant Sonde for vi their help with experiments while at IMEC. Special thanks are due to my daily mentor Dr. Eddy Simon for being patient with me and for his tremendous scientific and technical help. At this time I would also like to acknowledge all my peers for their valuable suggestions at all times. I would like to acknowledge the student government association and the division of graduate studies at UCF for numerous travel awards that helped me present research at various international conferences. I would also acknowledge professional organizations like IEEE, AVS and ECS for providing me with the opportunity for professional development. I Completing a Ph.D. dissertation is a humongous task that I would have not been able to complete with out the love and moral support of my parents, family and friends. Finally, with deep gratitude, I would like to thank my spiritual Guru for his divine guidance at all times. vii TABLE OF CONTENTS LIST OF FIGURES ....................................................................................................................... xi LIST OF TABLES....................................................................................................................... xvi LIST OF ACRONYMS/ABBREVIATIONS............................................................................. xvii CHAPTER ONE: INTRODUCTION............................................................................................. 1 CHAPTER TWO: LITERATURE REVIEW................................................................................. 4 2.1 CMOS and Its Scaling .......................................................................................................... 4 2.1.1 Conventional CMOS Scaling......................................................................................... 6 2.1.2 Non Conventional CMOS Scaling............................................................................... 10 2.2 High –κ Dielectrics ............................................................................................................. 18 2.2.1 Gate Stack Compatibility............................................................................................. 23 2.3 Metal Gates ......................................................................................................................... 26 2.3.1 Work Function ............................................................................................................. 28 2.3.2 Thermal and Chemical Stability .................................................................................. 29 2.3.3 High conductivity and high active electrical concentration......................................... 30 2.3.4 Compatibility with CMOS integration......................................................................... 31 2.3.5 Deposition technique ................................................................................................... 32 2.4 Germanium Devices............................................................................................................ 34 2.4.1 Mobility Enhancement in Silicon ................................................................................ 36 2.4.2 Germanium: Challenges and Opportunities................................................................. 39 CHAPTER THREE: METHODOLOGY ....................................................................................