WIDE I/O DRAM ARCHITECTURE UTILIZING PROXIMITY COMMUNICATION by Qawi IbnZayd Harvard A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical and Computer Engineering Boise State University October 2009 BOISE STATE UNIVERSITY GRADUATE COLLEGE DEFENSE COMMITTEE APPROVAL of the thesis submitted by Qawi IbnZayd Harvard We have read and discussed the thesis submitted by student Qawi IbnZayd Harvard, and we have also evaluated his presentation and response to questions during the final oral examination. We find that the student has passed the final oral examination, and that the thesis is satisfactory for a master’s degree and ready for any final modifications that we may explicitly require. ______________________ __________________________________________ Date R. Jacob Baker, Ph.D. Chair, Supervisory Committee ______________________ __________________________________________ Date Sin Ming Loo, Ph.D. Member, Supervisory Committee ______________________ __________________________________________ Date Thad Welch, Ph.D. Member, Supervisory Committee i BOISE STATE UNIVERSITY GRADUATE COLLEGE FINAL READING APPROVAL of the thesis submitted by Qawi IbnZayd Harvard To the Graduate College of Boise State University: I have read the thesis of Qawi IbnZayd Harvard in its final form and have found that (1) the modifications required by the defense committee are complete; (2) the format, citations, and bibliographic style are consistent and acceptable; (3) the illustrative materials including figures, tables, and charts are in place; and (4) the final manuscript is ready for submission to the Graduate College. ______________________ __________________________________________ Date R. Jacob Baker, Ph.D. Chair, Supervisory Committee Approved for the Graduate College: ______________________ __________________________________________ Date John R. Pelton, Ph.D. Dean of the Graduate College ii ACKNOWLEDGMENTS The author would like to acknowledge Dr. Jake Baker for his support. Dr. Baker has been the dominant contributor to my success, and this thesis would not be possible without his support. I would like to thank Dr. Kris Campbell for the financial support that she provided. I would like to thank Dr. Robert Drost for his guidance during my summer internship which led to the idea for this thesis. I’d like to thank my thesis committee for thoroughly reviewing the research and this thesis. Thanks Dr. Sin Loo and Dr. Welch. I would like to thank Ms. Welch for her assistance in proof reading this thesis. I would like to thank my family for their continued support and encouragement. I love you guys very much. iii ABSTRACT The bandwidth and power consumption of dynamic random access memory, used as the main memory of a computer system, impacts the computer’s execution rate even with the existence of a memory hierarchy. DRAM manufacturers focus on density increases due to the innate price per bit decline of main memory while processor manufacturers continually focus on boosting performance by increasing the number of instructions completed per second. This leads to a performance gap between the microprocessor and DRAM. Proximity communication promises to increase the I/O density of DRAM products while reducing the power consumption of the main memory system. This thesis develops and discusses the design of a memory system employing 4 Gb DRAM chips with a 64-bit wide communication bus using proximity communication. Technological roadblocks are analyzed and novel solutions are proposed. The proposed 4 Gb DRAM architecture can reduce the power consumption of a main memory system by 50% while increasing the bandwidth by 100%. The 4 Gb chip developed in this thesis measures 68.88 mm2 and has an array efficiency of 59.9%. These estimates are comparable to the 2012 International Technology Roadmap for Semiconductors’ estimates of 74 mm2 and 56%, respectfully. iv TABLE OF CONTENTS ACKNOWLEDGMENTS ............................................................................................. iii ABSTRACT .................................................................................................................. iv CHAPTER 1—INTRODUCTION ...................................................................................1 1.1 Organization ......................................................................................................2 1.2 Contributions of this Thesis ...............................................................................3 CHAPTER 2—PROXIMITY COMMUNICATION ........................................................4 2.1 Advantages ........................................................................................................5 2.1.1 I/O Density .................................................................................................6 2.1.2 Removal of Off-Chip Wires........................................................................7 2.1.3 Removal of ESD Structures ........................................................................8 2.1.4 Removal of the On-Die Termination ...........................................................8 2.1.5 Ease of Testability ......................................................................................9 2.2 Challenges ....................................................................................................... 10 2.2.1 Electronic Sensors for Measuring Misalignment ....................................... 10 2.2.2 Electronic Re-Alignment .......................................................................... 14 2.3 Summary ......................................................................................................... 17 CHAPTER 3—DRAM TRENDS .................................................................................. 19 3.1 Memory Gap ................................................................................................... 19 3.2 The DRAM Market and Technology ............................................................... 21 3.2.1 Selling Price ............................................................................................. 22 3.2.2 Wordline Scaling ...................................................................................... 25 3.2.3 Bitline Scaling .......................................................................................... 27 3.2.4 Contact Resistance Scaling ....................................................................... 28 3.3 DRAM Generations ......................................................................................... 28 3.3.1 Power ....................................................................................................... 29 3.3.2 Bandwidth ................................................................................................ 32 3.3.3 Bus Loading ............................................................................................. 35 3.4 Summary ......................................................................................................... 38 v CHAPTER 4—A 4 Gb DRAM ARCHITECTURE ....................................................... 39 4.1 Creating a 256 kb Array .................................................................................. 41 4.1.1 Memory Array ......................................................................................... 44 4.1.2 Periphery Circuitry................................................................................... 46 4.2 Creating a 256 Mb Array................................................................................. 49 4.3 Creating a 1 Gb Array ..................................................................................... 51 4.4 4 Gb DRAM Architecture ............................................................................... 52 4.5 Summary ........................................................................................................ 54 CHAPTER 5—A PROXIMITY COMMUNICATION DRAM ARCHITECTURE ....... 55 5.1 Architecture Decision...................................................................................... 55 5.1.1 Pad Moving and Centralization ................................................................ 56 5.1.2 512M Bit Bank Structures ........................................................................ 62 5.2 Side Mount Architecture ................................................................................. 63 5.3 Challenges ...................................................................................................... 65 5.3.1 Number of Metal Layers and Global I/O Routing ..................................... 65 5.3.2 Local I/O Routing .................................................................................... 67 5.4 Slice Architecture............................................................................................ 71 5.5 Summary ........................................................................................................ 73 CHAPTER 6—CONCLUSIONS .................................................................................. 77 BIBLIOGRAPHY ......................................................................................................... 79 vi LIST OF FIGURES Figure 2.1 Cross-sectional view of proximity communication .....................................4 Figure 2.2 Transmit and receive circuit diagram ..........................................................5 Figure 2.3 I/O density. .................................................................................................6