Field Programmable Gate Array (FPGA) Wae Wolf, FPGA Based “ste Desig , 2004, Prentice Hall. INTRODUCTION TO PROGRAMMABLE LOGIC • Programmable logic requires both hardware and software. • Programmable logic devices can be programmed to Perform specified logic functions by the manufacturer or by the user. • One advantage of programmable logic over fixed-function logic is that the devices use much less board space for an equivalent amount of logic. • Another advantage is that, with programmable logic, designs can be readily changed without rewiring or replacing components. • Also, a logic design can generally be implemented faster and with less cost with programmable logic than with fixed-function ICs. Types of Programmable logic Devices • Many types of programmable logic are available, ranging from small devices that can replace a few fixed-function devices to complex high-density devices that can replace thousands of fixed-function devices. • Two major categories of user-programmable logic are PLD (programmable logic device) and FPGA (field programmable gate array). • PLDs are either SPLDs (simple PLDs) or CPLDs (complex PLDs). Simple Programmable logic Devices • The SPLD was the original PLD and is still available for small-scale applications. • Generally, an SPLD can replace up to ten fixed-function ICs and their interconnections, depending on the type of functions and the specific SPLD. • Most SPLDs are in one of two categories: PAL and GAL. • A PAL (programmable array logic) is a device that can be programmed one time. It consists of a programmable array of AND gates and a fixed array of OR gates. • A GAL (generic array logic) is a device that is basically a PAL that can be reprogrammed many times. It consists of a reprogrammable array of AND gates and a fixed array of OR gates with programmable outputs. Complex Programmable logic Devices • Essentially, The CPLD is a device containing multiple SPLDs and can replace many fixed-function ICs. • Figure shows a basic CPLD block diagram with four logic array blocks (LABs) and a programmable interconnection array (PIA). • Depending on the specific CPLD, there can be from two to sixty-four LABs. • Each logic array block is roughly equivalent to one SPLD. • Generally, CPLDs can be used to implement any of the logic functions ,for example, decoders, encoders, multiplexers, demultiplexers, and adders. Field Programmable Gate Array • Field programmable gate arrays (FPGAs) are digital integrated circuits (ICs) that con tain configurable (programmable) blocks of logic along with configurable inter connects between these blocks. Design engineers can configure, or program, such devices to perform a tremendous variety of tasks. • The field programmable portion of the FPGA’s name refers to the fact that its programming takes place in the field (as opposed to devices whose internal functionality is hardwired by the manufacturer). • An FPGA is a regular structure of logic cells or modules and interconnect which is uder the desiger’s coplete cotrol. This eas the user ca desig, progra ad make changes to his circuit whenever he wants. • An FPGA is generally more complex and has a much higher density than a CPLD. • The logic blocks in an FPGA are not as complex as the logic array blocks (LABs) in a CPLD, but generally there are many more of them. • FPGAs can be used to implement any logical function that an ASIC could perform. RATHER YOU CAN ALSO BUILD MICROs USING FPGAs. • FPGA are basically made up for the home integration, the user has all the power of development and changing the logic using very versatile interconnects between logic elements. • FPGA consist of millions of transistor logic and thousands of logic block elements, so it is an ultra large scale integration. • Compared to ASIC, FPGAs are home programmable and can be designed using simple software algorithms. • The three basic elements in an FPGA are the logic block, the programmable interconnections, and the input/output (I/O) blocks. • When the logic blocks are relatively simple, the FPGA architecture is called fine- grained. • When the logic blocks are larger and more complex, the architecture is called coarse-grained. • The I/O blocks are on the outer edges of the structure and provide individually selectable input, output, or bidirectional access to the outside world. • The distributed programmable interconnection matrix provides for interconnection of the logic blocks and connection to inputs and outputs. • Large FPGAs can have tens of thousands of logic blocks in addition to memory and other resources. • A typical FPGA ball-grid array package is shown here, these types of packages can have over 1000 input and output pins. Logic Types • Logic functions implemented in Look Up Table LUTs • Truth Tables. • Flip Flop • Registers • Clocked Storage Elements • Multiplexers Logic Blocks FPGAs are built from one basic "logic-cell", duplicated hundreds or thousands of time. A logic-cell is basically a small lookup table ("LUT"), a D-flipflop and a 2-to-1 mux (to bypass the flipflop if desired). The LUT is like a small RAM that can implement any logic function. It has typically a few inputs (4 in the drawing above), so for example an AND gate with 3 inputs, whose result is then OR-ed with another input would fit in one 4-inputs LUT Look Up Tables (LUTs) • LUT contains Memory Cells to implement small logic functions • Each Cell holds 0 or 1 • Programmed with outputs of truth table • Input select content of one of the cells as output. Interconnect Each logic-cell can be connected to other logic- cells through interconnect resources (wires/muxes placed around the logic-cells). Each cell can do little, but with lots of them connected together, complex logic functions can be created. IO-Cells The interconnect wires also go to the boundary of the device where I/O cells are implemented and connected to the pins of the FPGAs. Dedicated routing/carry chains In addition to general-purpose interconnect resources, FPGAs have fast dedicated lines in between neighboring logic cells. The most common type of fast dedicated lines are "carry chains". Carry chains allow creating arithmetic functions (like counters and adders) efficiently (low logic usage & high operating speed). Internal RAM In addition to logic, all new FPGAs have dedicated blocks of static RAM distributed among and controlled by the logic elements. Designing Logic with FPGAs The Programming Process An SPLD, CPLD, or FPGA can be thought of as a "blank slate" on which you implement a specified circuit or system design using a certain process. This process requires a software development package installed on a computer to implement a circuit design in the programmable chip. The computer must be interfaced with a development board or programming fixture containing the device. Several steps, called the design flow are involved in the process of implementing a digital logic design in a programmable logic device. A block diagram of a typical programming process is shown here, as indicated, the design flow has access to a design library. Design Entry: This is the first programming step. The circuit or system design must be entered into the design application software using text-based entry, graphic entry (schematic capture), or state diagram description. -Design entry is device independent. -Text-based entry is accomplished with a hardware description language (HDL) such as VHDL, Verilog. - Graphic (schematic) entry allows pre-stored logic functions from a library to be selected, placed on the screen, and then interconnected to create a logic design. - State diagram entry requires specification of both the states through which a sequential logic circuit progresses and the conditions that produce each state change. -Once a design has been entered, it is compiled. Functional Simulation: The entered and compiled design is simulated by software to confirm that the logic circuit functions as expected. -The simulation will verify that correct outputs are produced for a specified set of inputs. -A device-independent software tool for doing this is generally called a waveform editor: Any flaws demonstrated by the simulation would be corrected by going back to design entry and making appropriate changes. Synthesis: Synthesis is where the design is translated into a netlist, which has a standard form and is device independent. - During the synthesis phase of the design flow, the design is optimized in terms of minimizing the number of gates. replacing logic elements with other logic elements that can perform the same function more efficiently, and eliminating any redundant logic. - The final output from the synthesis phase is a netlist that describes the optimized version of the logic circuit. - A netlist is basically a connectivity list that describes components and how they are connected together. Implementation: Implementation is where the logic structures described by the netlist are mapped into the actual structure of the specific device being programmed. The implementation process is called fitting or place and route and results in an output called a bit stream, which is device dependent. Timing Simulation: This step comes after the design is mapped into the specific device. The timing simulation is basically used to confirm that there are no design flaws or timing problems due to propagation delays. Download: Once a bit stream has been generated for a specific programmable device, it has to be downloaded to the device to implement the software design in hardware. Application Specific Integrated Circuits (ASICSs) • An ASIC is basically an integrated circuit designed specifically for a special purpose or application. • Strictly speaking, this also implies that an ASIC is built only for one and only one customer. • An example of an ASIC is an IC designed for a specific line of cellular phones of a company, whereby no other products can use it except the cell phones belonging to that product line.