Intel® Quartus® Prime Pro Edition User Guide Partial Reconfiguration Updated for Intel® Quartus® Prime Design Suite: 19.3 Subscribe UG-20136 | 2019.11.18 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Creating a Partial Reconfiguration Design.......................................................................4 1.1. Partial Reconfiguration Terminology..........................................................................5 1.2. Partial Reconfiguration Process Sequence..................................................................6 1.3. Internal Host Partial Reconfiguration........................................................................ 7 1.4. External Host Partial Reconfiguration........................................................................ 9 1.5. Partial Reconfiguration Design Considerations............................................................9 1.5.1. Partial Reconfiguration Design Guidelines.................................................... 11 1.5.2. PR File Management.................................................................................12 1.5.3. Evaluating PR Region Initial Conditions....................................................... 16 1.5.4. Creating Wrapper Logic for PR Regions........................................................16 1.5.5. Creating Freeze Logic for PR Regions.......................................................... 17 1.5.6. Resetting the PR Region Registers.............................................................. 18 1.5.7. Promoting Global Signals in a PR Region..................................................... 19 1.5.8. Planning Clocks and other Global Routing.................................................... 20 1.5.9. Implementing Clock Enable for On-Chip Memories with Initialized Contents..... 21 1.6. Partial Reconfiguration Design Flow........................................................................ 23 1.6.1. Step 1: Identify Partial Reconfiguration Resources........................................ 25 1.6.2. Step 2: Create Design Partitions................................................................ 26 1.6.3. Step 3: Floorplan the Design..................................................................... 28 1.6.4. Step 4: Add the Partial Reconfiguration Controller Intel FPGA IP..................... 31 1.6.5. Step 5: Define Personas............................................................................33 1.6.6. Step 6: Create Revisions for Personas.........................................................33 1.6.7. Step 7: Compile the Base Revision and Export the Static Region.....................35 1.6.8. Step 8: Setup PR Implementation Revisions................................................ 37 1.6.9. Step 9: Program the FPGA Device.............................................................. 38 1.7. Hierarchical Partial Reconfiguration.........................................................................43 1.8. Partial Reconfiguration Design Timing Analysis.........................................................44 1.8.1. Running Timing Analysis on Aggregate Revisions..........................................44 1.9. Partial Reconfiguration Design Simulation................................................................45 1.9.1. Partial Reconfiguration Simulation Flow....................................................... 46 1.10. Partial Reconfiguration Design Debugging..............................................................50 1.10.1. Debugging PR Designs with Signal Tap Logic Analyzer................................. 50 1.11. PR Bitstream Security Verification (Intel Stratix 10 and Intel Agilex Designs)..............51 1.11.1. PR Bitstream Security Use Case (Intel Stratix 10 and Intel Agilex Designs).... 52 1.11.2. Using PR Bitstream Security Verification (Intel Stratix 10 and Intel Agilex Designs)................................................................................................. 52 1.12. PR Bitstream Compression and Encryption (Intel Arria 10 and Intel Cyclone 10 GX Designs).......................................................................................................... 54 1.12.1. Generating an Encrypted PR Bitstream (Intel Arria 10 or Intel Cyclone 10 GX Designs)............................................................................................ 54 1.12.2. Clock-to-Data Ratio for Bitstream Encryption and Compression (Intel Arria 10 or Intel Cyclone 10 GX Designs).....................................................55 1.12.3. Data Compression Comparison.................................................................56 1.13. Avoiding PR Programming Errors.......................................................................... 57 1.14. Exporting a Version-Compatible Compilation Database for PR Designs....................... 59 1.14.1. Version-Compatible Database Flow for PR Designs...................................... 60 1.14.2. Generating a Version-Compatible Compilation Database for PR Designs......... 60 Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration Send Feedback 2 Contents 1.15. Creating a Partial Reconfiguration Design Revision History....................................... 61 2. Partial Reconfiguration Solutions IP User Guide........................................................... 64 2.1. Internal and External PR Host Configurations...........................................................64 2.2. Partial Reconfiguration Controller Intel FPGA IP........................................................67 2.2.1. Memory Map........................................................................................... 67 2.2.2. Parameters............................................................................................. 68 2.2.3. Ports...................................................................................................... 69 2.2.4. Timing Specifications................................................................................71 2.3. Partial Reconfiguration Controller Intel Arria 10/Cyclone 10 FPGA IP........................... 72 2.3.1. Slave Interface........................................................................................ 72 2.3.2. Reconfiguration Sequence......................................................................... 73 2.3.3. Interrupt Interface................................................................................... 73 2.3.4. Parameters............................................................................................. 74 2.3.5. Ports...................................................................................................... 76 2.3.6. Timing Specifications................................................................................80 2.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation...................81 2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation........................... 81 2.3.9. PR Control Block Signals........................................................................... 83 2.3.10. Configuring an External Host for Intel Arria 10 or Intel Cyclone 10 GX Designs.................................................................................................. 86 2.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP........................ 89 2.4.1. Parameters............................................................................................. 90 2.4.2. Ports...................................................................................................... 90 2.4.3. Configuring an External Host for Intel Stratix 10 or Intel Agilex Designs.......... 91 2.5. Partial Reconfiguration Region Controller Intel FPGA IP..............................................92 2.5.1. Registers................................................................................................ 93 2.5.2. Parameters............................................................................................. 96 2.5.3. Ports...................................................................................................... 97 2.6. Avalon-MM Partial Reconfiguration Freeze Bridge Intel FPGA IP.................................. 99 2.6.1. Parameters............................................................................................101 2.6.2. Interface Ports.......................................................................................103 2.7. Avalon-ST Partial Reconfiguration Freeze Bridge Intel FPGA IP..................................108 2.7.1. Parameters............................................................................................110 2.7.2. Ports ................................................................................................... 112 2.8. Generating and Simulating Intel FPGA IP...............................................................115 2.8.1. Generating IP Cores (Intel Quartus Prime Pro Edition)................................. 115 2.8.2. Running the Freeze Bridge Update script................................................... 117 2.8.3. IP Core Generation Output (Intel Quartus Prime Pro Edition)........................ 118 2.8.4. Intel Arria 10 and Intel Cyclone 10 GX PR Control Block Simulation Model......121 2.8.5. Generating the PR Persona Simulation Model............................................. 123 2.9. Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration Archive............... 124 2.10. Partial Reconfiguration