Università di Pisa Corso di Laurea Magistrale in Ingegneria Elettronica Tesi di Laurea Magistrale Security in automotive microcontrollers of next generation Candidato: Giorgio Boccini Relatori: Prof. Ing. Luca Fanucci …………………………………… …………………………………… Ing. Massimiliano Donati ……………………………………… Anno accademico 2013/2014 1 Summary Chapter 1 Introduction ...................................................................................................................................................................... 5 Chapter 2 Security ................................................................................................................................................................................ 7 2.1 Information security .......................................................................................................................................................... 8 2.2 IT security ................................................................................................................................................................................ 9 2.3 Embedded security .......................................................................................................................................................... 11 2.3.1 Embedded Security vs. General IT Security .............................................................................................. 11 2.3.2 Cryptographic Algorithms in Constraint Environments .................................................................... 12 2.3.3 Physical Security: Side Channel Attacks and Reverse Engineering.............................................. 13 2.3.4 Digital Rights Management (DRM) ............................................................................................................... 13 2.4 Automotive Applications and IT Security ............................................................................................................ 14 Chapter 3 Automotive Security .................................................................................................................................................. 18 3.1 Experimental Security Analysis of a Modern Automobile .......................................................................... 18 3.2 Comprehensive Experimental Analyses of Automotive Attack Surfaces ............................................ 26 Chapter 4 State of art ....................................................................................................................................................................... 32 4.1 Evolution of the standard solutions ........................................................................................................................ 32 4.1.1 SHE ................................................................................................................................................................................. 32 4.1.2 Project EVITA ........................................................................................................................................................... 37 4.2 Comparison table .............................................................................................................................................................. 70 Chapter 5 CAN protocol .................................................................................................................................................................. 73 5.1 Basic Concepts.................................................................................................................................................................... 73 5.1.1 Layered Structure of a CAN Node .................................................................................................................. 74 5.1.2 Frame Structure ...................................................................................................................................................... 75 5.2 CAN security features ..................................................................................................................................................... 77 5.3 Analysis of the security level requested ............................................................................................................... 79 Chapter 6 Advance Encryption Standard .............................................................................................................................. 82 6.1 Introduction ........................................................................................................................................................................ 82 6.2 Overview of the AES Algorithm ................................................................................................................................. 84 2 6.3 Some Mathematics: A Brief Introduction to Galois Fields ........................................................................... 87 6.3.1 Existence of Finite Fields .................................................................................................................................... 87 6.3.2 Prime Fields .............................................................................................................................................................. 88 6.3.3 Extension Fields GF (2m)..................................................................................................................................... 90 6.3.4 Addition and Subtraction in GF (2m) ............................................................................................................ 91 6.3.5 Multiplication in GF(2m)...................................................................................................................................... 92 6.3.6 Inversion in GF (2m) .............................................................................................................................................. 94 6.4 Internal Structure of AES .............................................................................................................................................. 95 6.4.1 Byte Substitution Layer....................................................................................................................................... 96 6.4.2 Diffusion Layer ........................................................................................................................................................ 99 6.4.3 Key Addition Layer ............................................................................................................................................. 101 6.4.4 Key Schedule .......................................................................................................................................................... 101 6.4.5 Decryption .............................................................................................................................................................. 104 Chapter 7 AES-128 HW Implementation ............................................................................................................................ 109 7.1 System Verilog model .................................................................................................................................................. 109 7.2 Hardware module.......................................................................................................................................................... 110 7.2.1 Overview .................................................................................................................................................................. 110 7.2.2 key_schedule module ........................................................................................................................................ 111 7.2.3 Encryption/Decryption module .................................................................................................................. 113 7.3 Functional simulations ............................................................................................................................................... 116 7.4 Synthesis ............................................................................................................................................................................ 118 7.4.1 Version 1 .................................................................................................................................................................. 118 7.4.2 Version 2 .................................................................................................................................................................. 120 7.5 Conclusion ......................................................................................................................................................................... 122 Appendix ................................................................................................................................................................................................ 123 System Verilog model ................................................................................................................................................................. 123 System Verilog test bench .......................................................................................................................................................