15-398 Introduction to Nanotechnology Outline • Transistor theory • Transistor reality Transistors and Scaling • Scaling Seth Copen Goldstein [email protected] CMU Adapted from “Intro to CMOS VLSI Design, Harris lecture6 15-398 © 2004-5 Seth Copen Goldstein 1 lecture6 15-398 © 2004-5 Seth Copen Goldstein 2 nMOS Transistor MOS Capacitor • Four terminals: gate, source, drain, body • Gate and body form MOS capacitor • Gate – oxide – body stack looks like a capacitor • Operating modes polysilicon gate V < 0 g silicon dioxide insulator – Gate and body are conductors – Accumulation + - p-type body –SiO2 (oxide) is a very good insulator –Depletion – Called metal – oxide – semiconductor (MOS) capacitor (a) –Inversion – Even though gate is 0 < V < V SourceGate Drain g t depletion region no longer made of metal Polysilicon + - SiO2 (b) n+ n+ Vg > Vt inversion region p bulk Si + - depletion region (c) lecture6 15-398 © 2004-5 Seth Copen Goldstein 3 lecture6 15-398 © 2004-5 Seth Copen Goldstein 4 Terminal Voltages nMOS Cutoff Vg + • Mode of operation depends on Vg, Vd, Vs + Vgs Vgd • No channel –Vgs = Vg –Vs - - –Vgd = Vg –Vd V V •Ids = 0 s - + d Vds –Vds = Vd –Vs = Vgs -Vgd • Source and drain are symmetric diffusion terminals V = 0 V gs + g + gd – By convention, source is terminal at lower voltage - - –Hence Vds ≥ 0 s d • nMOS body is grounded. First assume source is 0 too. n+ n+ • Three regions of operation p-type body – Cutoff b – Linear – Saturation lecture6 15-398 © 2004-5 Seth Copen Goldstein 5 lecture6 15-398 © 2004-5 Seth Copen Goldstein 6 nMOS Linear nMOS Saturation • Channel forms • Current flows from d to s (e- from s to d) • Channel pinches off •I independent of V •Ids ↑ as Vds ↑ ds ds V > V gs t V = V •Similar to + g + gd gs • We say current saturates - - linear resistor s d V = 0 n+ n+ ds p-type body V > V b gs t V < V + g + gd t - - V > V s Ids gs t V > V > V d + g + gs gd t - - n+ n+ I V > V -V s d ds ds gs t p-type body n+ n+ 0 < V < V -V ds gs t b p-type body b lecture6 15-398 © 2004-5 Seth Copen Goldstein 7 lecture6 15-398 © 2004-5 Seth Copen Goldstein 8 I-V Characteristics Channel Charge • In Linear region, Ids depends on • MOS structure looks like parallel plate – How much charge is in the channel? capacitor while operating in inversion –Gate –oxide –channel – How fast is the charge moving? •Qchannel = gate Vg polysilicon ++ gate V C V source gs g gd drain W V - - V t s channel d ox n+- + n+ V L SiO2 gate oxide ds n+ n+ (good insulator, ε = 3.9) ox p-type body p-type body lecture6 15-398 © 2004-5 Seth Copen Goldstein 9 lecture6 15-398 © 2004-5 Seth Copen Goldstein 10 Channel Charge Channel Charge • MOS structure looks like parallel plate • MOS structure looks like parallel plate capacitor while operating in inversion capacitor while operating in inversion –Gate –oxide –channel –Gate –oxide –channel •Qchannel = CV •Qchannel = CV •C = •C = Cg = εoxWL/tox = CoxWL Cox = εox / tox •V = gate gate Vg Vg polysilicon ++ polysilicon ++ gate V C V gate V C V source gs g gd drain source gs g gd drain W W V - - V V - - V t s channel d t s channel d ox n+- + n+ ox n+- + n+ V V L SiO2 gate oxide ds L SiO2 gate oxide ds n+ n+ (good insulator, ε = 3.9) n+ n+ (good insulator, ε = 3.9) ox p-type body ox p-type body p-type body p-type body lecture6 15-398 © 2004-5 Seth Copen Goldstein 11 lecture6 15-398 © 2004-5 Seth Copen Goldstein 12 Channel Charge Carrier velocity • MOS structure looks like parallel plate • Charge is carried by e- capacitor while operating in inversion • Carrier velocity v proportional to lateral E- –Gate –oxide –channel field between source and drain •Qchannel = CV • v = •C = Cg = εoxWL/tox = CoxWL Cox = εox / tox •V = Vgc –Vt = (Vgs –Vds/2) – Vt gate Vg polysilicon ++ gate V C V source gs g gd drain W V - - V t s channel d ox n+- + n+ V L SiO2 gate oxide ds n+ n+ (good insulator, ε = 3.9) ox p-type body p-type body lecture6 15-398 © 2004-5 Seth Copen Goldstein 13 lecture6 15-398 © 2004-5 Seth Copen Goldstein 14 Carrier velocity Carrier velocity • Charge is carried by e- • Charge is carried by e- • Carrier velocity v proportional to lateral E- • Carrier velocity v proportional to lateral E- field between source and drain field between source and drain • v = μE μ called mobility • v = μE μ called mobility •E = •E = Vds/L • Time for carrier to cross channel: – t = lecture6 15-398 © 2004-5 Seth Copen Goldstein 15 lecture6 15-398 © 2004-5 Seth Copen Goldstein 16 Carrier velocity nMOS Linear I-V • Charge is carried by e- • Now we know • Carrier velocity v proportional to lateral E- – How much charge Qchannel is in the channel field between source and drain – How much time t each carrier takes to cross • v = μE μ called mobility •E = Vds/L Ids = • Time for carrier to cross channel: – t = L / v lecture6 15-398 © 2004-5 Seth Copen Goldstein 17 lecture6 15-398 © 2004-5 Seth Copen Goldstein 18 nMOS Linear I-V nMOS Linear I-V • Now we know • Now we know – How much charge Qchannel is in the channel – How much charge Qchannel is in the channel – How much time t each carrier takes to cross – How much time t each carrier takes to cross Q β: gain factor Qchannel channel I = Ids = Depends on: ds t t • Process = W ⎛⎞V =−−μCVV⎜⎟ds V • geometry ox L ⎝⎠gs t2 ds W ⎛⎞Vds =−−β ⎜⎟VV V βμ = Cox ⎝⎠gs t2 ds L lecture6 15-398 © 2004-5 Seth Copen Goldstein 19 lecture6 15-398 © 2004-5 Seth Copen Goldstein 20 nMOS Saturation I-V nMOS Saturation I-V •If Vgd < Vt, channel pinches off near drain •If Vgd < Vt, channel pinches off near drain –When Vds > Vdsat = Vgs –Vt –When Vds > Vdsat = Vgs –Vt • Now drain voltage no longer increases • Now drain voltage no longer increases current current ⎛⎞V I = I =−−β ⎜⎟VVdsat V ds ds ⎝⎠gs t2 dsat lecture6 15-398 © 2004-5 Seth Copen Goldstein 21 lecture6 15-398 © 2004-5 Seth Copen Goldstein 22 nMOS Saturation I-V nMOS I-V Summary st •If Vgd < Vt, channel pinches off near drain • Shockley 1 order transistor models –When Vds > Vdsat = Vgs –Vt • Now drain voltage no longer increases current ⎧ ⎛⎞Vdsat ⎪ 0 VV< cutoff I =−−β ⎜⎟VV V gs t ds ⎝⎠gs t2 dsat ⎪ ⎪ ⎛⎞Vds 2 IVVVVVds=−−⎨β ⎜⎟ gs t ds ds < dsat linear β ⎝⎠2 =−()VVgs t ⎪ 2 ⎪ β 2 ()VVgs−> t VV ds dsat saturation ⎩⎪ 2 lecture6 15-398 © 2004-5 Seth Copen Goldstein 23 lecture6 15-398 © 2004-5 Seth Copen Goldstein 24 Example pMOS I-V • Consider a 0.6 μm process • All dopings and voltages are inverted for pMOS – From AMI Semiconductor • Mobility μp is determined by holes –t = 100 Å ox 2.5 – Typically 2-3x lower than that of electrons μn Vgs = 5 – μ = 350 cm2/V*s 2 2 –120 cm/V*s in AMI 0.6 μm process –Vt = 0.7 V 1.5 • Thus pMOS must be wider to provide same Vgs = 4 •Plot Ids vs. Vds (mA) current ds ds I 1 V = 3 –Vgs = 0, 1, 2, 3, 4, 5 gs 0.5 – Use W/L = 4/2 λ Vgs = 2 V = 1 0 gs 0 1 2 3 4 5 −14 V WWW⎛⎞3.9•⋅ 8.85 10 ⎛⎞ 2 ds βμ==CAVox ()350⎜⎟−8 ⎜⎟ = 120 μ / LLL⎝⎠100⋅ 10 ⎝⎠ lecture6 15-398 © 2004-5 Seth Copen Goldstein 25 lecture6 15-398 © 2004-5 Seth Copen Goldstein 26 Ideal Transistor I-V Ideal nMOS I-V Plot • Shockley 1st order transistor models • 180 nm TSMC process I (μA) • Ideal Models ds 400 – β = 155(W/L) μA/V2 Vgs = 1.8 300 ⎧ –Vt = 0.4 V ⎪ 0 VVgs< t cutoff –VDD = 1.8 V V = 1.5 ⎪ 200 gs ⎪ ⎛⎞Vds V = 1.2 IVVVVV=−−β <linear gs ds⎨ ⎜⎟ gs t2 ds ds dsat 100 ⎝⎠ V = 0.9 ⎪ gs Vgs = 0.6 2 0 Vds ⎪ β 0 0.3 0.6 0.9 1.2 1.5 1.8 ()VVgs−> t VV ds dsat saturation ⎩⎪ 2 lecture6 15-398 © 2004-5 Seth Copen Goldstein 27 lecture6 15-398 © 2004-5 Seth Copen Goldstein 28 Simulated nMOS I-V Plot Simulated nMOS I-V Plot • 180 nm TSMC process • 180 nm TSMC process • BSIM 3v3 SPICE models • BSIM 3v3 SPICE models I (μA) I (μA) •What differs? ds •What differs? ds 250 V = 1.8 250 V = 1.8 gs – Less ON current gs 200 200 V = 1.5 V = 1.5 gs – No square law gs 150 150 Vgs = 1.2 – Current increases Vgs = 1.2 100 in saturation 100 Vgs = 0.9 Vgs = 0.9 50 50 Vgs = 0.6 Vgs = 0.6 0 0 0 0.3 0.6 0.9 1.2 1.5 0 0.3 0.6 0.9 1.2 1.5 Vds Vds lecture6 15-398 © 2004-5 Seth Copen Goldstein 29 lecture6 15-398 © 2004-5 Seth Copen Goldstein 30 Velocity Saturation Vel Sat I-V Effects 2 • We assumed carrier velocity is • Ideal transistor ON current increases with VDD proportional to E-field 2 W ()VVgs− t β 2 – v = μE = μV /L Ids==−μCVVox () gs t lat ds L 22 • At high fields, this ceases to be true • Velocity-saturated ON current increases with – Carriers scatter off atoms ν ν sat VDD – Velocity reaches vsat • Electrons: 6-10 x 106 cm/s Ids=−CWVox( gs V t ) v max •Holes: 4-8 x 106 cm/s ν / 2 –Better model sat • Real transistors are partially velocity saturated μElat vvE=⇒=μ slope = μ – Approximate with α-power law model E sat sat 1+ lat α 0 –I ∝ V E 3E ds DD sat 0 Esat 2Esat sat Elat – 1 < α < 2 determined empirically lecture6 15-398 © 2004-5 Seth Copen Goldstein 31 lecture6 15-398 © 2004-5 Seth Copen Goldstein 32 α-Power Model Channel Length Modulation ⎧ 0cutoffVVgs< t ⎪ β α ⎪ V Idsat=−PVV c() gs t ds 2 IIds=<⎨ dsat VV ds dsat linear • Reverse-biased p-n junctions form a depletion ⎪ Vdsat α /2 ⎪ VPVVdsat=− v() gs t region ⎩ IVVdsat ds> dsat saturation – Region between n and p with no carriers Ids (μA) Simulated – Width of depletion Ld region grows with reverse bias 400 α-law Shockley –Leff = L – Ld 300 •Shorter L gives more current eff V Vgs = 1.8 GND DD VDD –Ids increases with Vds SourceGate Drain 200 Depletion Region Vgs = 1.5 –Even in saturation Width: Ld 100 Vgs = 1.2 V = 0.9 L gs n+ L n+ V = 0.6 eff 0 gs 0 0.3 0.6 0.9 1.2 1.5 1.8 p GND bulk Si Vds lecture6 15-398 © 2004-5 Seth Copen Goldstein 33 lecture6 15-398 © 2004-5 Seth Copen Goldstein 34 OFF Transistor Behavior Leakage Sources • What about current in cutoff?