18 CMOS Static NAND Gate n Second switching condition: VA = VDD and VB switches from 0 to VDD VDD I V D DD M3 M4 = VGS1 VDD VM V M M2 = − = VGS2 VM VDS1 + ID1 ID2 M1 VDS1 _ VDS (a) (b) At VB = VM, the current through M1 and M2 is higher than when VA = VB since the gate voltage on M1 is now VDD and its VDS1 must be smaller --> VGS2 is larger. Effective kn is increased. At VB = VM, only M4 is conducting current --> only half the current as for previous switching condition. Effective kp is that of device M4 n Result: VM is 0.3-0.5 V lower than for VA = VB switching condition, for typical dimensions EECS 105 Fall 1998 Lecture 18 NAND Gate Transfer Functions n SPICE is useful to solve for the transfer functions under the various switching conditions (see Ex. 5.7). Note that the backgate effect means that the curves when VA switches and when VB switches are not identical. VOUT (V) Transfer Functions 5.0 4.0 B SWITCHES A SWITCHES 3.0 A & B SWITCH 2.0 1.0 0.0 0.0 1.0 2.0 3.0 4.0 5.0 VIN (V) n Results: setting kn = 2 kp results in VM approximately VDD/2. EECS 105 Fall 1998 Lecture 18 CMOS NAND Gate Transient Analysis n Worst-case situation for low-to-high transition: only one of the p-channel transistors is switching (say M4): kp 2 –I ==–I ----- ()V + V Dp D4 2 DD Tp n For high-to-low transition, consider M1 and M2 in series with effective length at 2Ln (worst-case since current is lowest with VA = VB) 2kn 2 I==I I =µ C []W ⁄22()L ()V– V =----- ()V – V Dn D1 D2 n ox n n DD Tn 4DD Tn n For equal propagation delays, we require IDn = -IDp kk ----n- = ----p- --> k = 2k 42 n p The factor of 2 mobility difference between the p and n channels indicates that (W/L)n = (W/L)p (2 input NAND gate) n For an M-input NAND gate, we find that (W/L)n = (M/2) (W/L)p Note: NOR gates suffer from a factor of 2M between the n- and p-channel ratios which makes them unattractive for large fan-in gates EECS 105 Fall 1998 Lecture 18 Transistor Sizing (Example) VDD B A C D Y A D (W/L)0 B C GND Logic function Y= D+[A*(B+C)] EECS 105 Fall 1998 Lecture 18 CMOS Dynamic Logic n Static NOR gate VDD A M4 B M3 Q A M1 B M2 CL Idea: n-channel and p-channel devices separately perform the same logic function. replace p-channels with a resistor --> QAB=+ replace n-channels with a resistor --> QAB= ... two functions are identical by DeMorgan’s Theorem n Let n-channels perform the logic and get rid of the pull-up devices (or vice versa) EECS 105 Fall 1998 Lecture 18 n-Channel CMOS Dynamic Logic φ n clock signal (t) charges up load capacitance through MP (P = precharge) when it transitions from high to low; ME (E = evaluate) is cutoff and prevents any discharge path of CL through logic function transistors. n clock signal goes high --> MP is cutoff, ME conducts --> CL discharges if one of the logic transistors has a high input. VDD φ φ MP + evaluate evaluate VDD A B C M CL VOUT precharge − 0 t Logic φ M Function E (a) (b) n Payoffs: 1. large fan-in NOR gates without huge p-channel load devices (also, avoids backgate effect on loads) 2. tends to be fast due to smaller load capacitances n Drawback: 1. clock is essential to refresh logic level stored on CL, which complicates the design EECS 105 Fall 1998 Lecture 18 n-Channel Dynamic Logic Propagation Delays n Consider “tPLH” to be the time required to pre-charge the output node Precharge Circuit (tPLH) VDD M φ = 0 P VOUT (t = 0) = 0 V CL A B M φ = 0 ME (cutoff) n Charging current kp 2 –I =----- ()V + V Dp 2 DD Tp EECS 105 Fall 1998 Lecture 18 n-Channel Dynamic Logic Propagation Delays n Consider “tPHL” to be the worst-case time to evaluate the logical function after clock goes high. Evaluate Circuit (tPHL) (only one input high) VDD φ = 5 V MP (cutoff) VOUT (t = 0) = 0 V CL 5 V 0 V 0 V φ = 5 V ME n Discharging current: assume (W/L)E = (W/L)A = ... (W/L)M and note that the transistors are in series -->effective value is kn / 2 kn 2 I =µ C ----- ()V – V Dn n ox4 DD Tn EECS 105 Fall 1998 Lecture 18 Boolean Functions in Dynamic Logic n Examples: VDD VDD φ MP φ ME Q A A B C D B C Q φ MP φ ME (a) (b) n (a) n-channel dynamic logic QAB=()+C n (b) p-channel dynamic logic The output is “pre-discharged” to zero by MP and is only charged if there is a path through the logic transistors when the clock goes low and ME conducts. QABCD= ++ EECS 105 Fall 1998 Lecture 18 CMOS Transmission Gates n Need: “gate” signals by having a series switch that can be shorted or open- circuited. C C IN OUT IN OUT C C (a) (b) n Why n-channel and p-channel in parallel? Only one device (say, n-channel): can’t pass an input voltage > VDD - VTn, since device will enter the cutoff region . G 5 V G 0 V D S D S 5 V − V − 5 V Tn 0 V 0 V VTp B B 0 V 5 V (a) charge-up (b) discharge EECS 105 Fall 1998 Lecture 18 Pass Transistor Logic n Advantages: reduced transistor count and higher speed compared with static CMOS n Disadvantage: reduced noise margins B B A B B OUT B OUT B A (a) (b) Switching Network (c) EECS 105 Fall 1998 Lecture 18.