HIGH-SPEED MULTI OPERAND ADDITION UTILIZING FLAG BITS BY VIBHUTI DAVE DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Engineering in the Graduate College of the Illinois Institute of Technology Approved _________________________ Adviser _________________________ Co – Adviser Chicago, Illinois May 2007 ACKNOWLEDGEMENT I would like to thank my mentor Dr. Erdal Oruklu for his constant support and undue faith in me. I highly appreciate the time he has invested during my research and for the completion of this dissertation. This dissertation would not have been possible without Dr. Jafar Saniie, my advisor and his attempts to challenge me throughout my academic program, encouraging me when I was successful and pushing me to do better when I fell short. I would also like to thank Dr. Dimitrios Velenis and Dr. James Stine for their constructive criticism about my work and helping me to perform better. A special thanks to the committee members for their support and time. iii TABLE OF CONTENTS Page ACKNOWLEDGEMENT ....................................................................................... iii LIST OF TABLES ................................................................................................... vi LIST OF FIGURES ................................................................................................. vii ABSTRACT ............................................................................................................. x CHAPTER 1. INTRODUCTION .............................................................................. 1 1.1 Motivation .............................................................................. 1 1.2 Goals ........................................................................................... 2 1.3 Structure of Thesis...................................................................... 3 2. DESIGN CRITERIA AND IMPLICATIONS .................................... 5 2.1 Arithmetic Operations and Units ........................................... 5 2.2 Circuit and Layout Design Techniques ...................................... 8 2.3 Automated Circuit Synthesis and Optimization ......................... 11 2.4 Circuit Complexity and Performance Measures......................... 13 2.5 Summary..................................................................................... 16 3. ADDER DESIGNS.................................................................................. 18 3.1 1 - Bit Adders.............................................................................. 18 3.2 Carry Propagate Adders.............................................................. 21 3.3 Carry Select Adders .................................................................... 22 3.4 Carry Skip Adders ...................................................................... 25 3.5 Carry Save Adders...................................................................... 29 3.6 Parallel Prefix Adders ................................................................ 30 3.7 Summary..................................................................................... 39 4. LOGICAL EFFORT ........................................................................... 40 4.1 Delay in a Logic Gate ................................................................. 40 4.2 Multistage Logic Networks........................................................ 44 4.3 Choosing the Best Number of Stages….. ................................... 48 iv 4.4 Summary of the Method…. ....................................................... 48 4.5 Summary .................................................................................... 50 5. FLAGGED PREFIX ADDITION............................................................ 52 5.1 Background Theory of Fagged Prefix Addition ......................... 53 5.2 Implementation of a Flagged Prefix Adder ................................ 55 5.3 Modifications to a Prefix Adder…....... ...................................... 56 5.4 Delay Performance of a Flagged Prefix Adder........................... 57 5.5 Fixed Point Arithmetic Applications….. .................................... 59 5.6 Summary ..................................................................................... 62 6. THREE - INPUT ADDITION................................................................. 63 6.1 Carry - Save Adders ............................................................... 63 6.2 Multi - Operand Adders.............................................................. 64 6.3 Flag Logic Computation ........................................................ 67 6.4 Constant Addition....................................................................... 70 6.5 Three - Input Addition ........................................................... 71 6.6 Gate Count ................................................................................. 73 6.7 Summary ................................................................................ 77 7. ANALYSIS AND SIMULATION .......................................................... 80 7.1 Logical Effort ......................................................................... 80 7.2 Simulation Results...................................................................... 88 7.3 Summary ................................................................................ 93 8. CONCLUSIONS AND FUTURE WORK .............................................. 106 BIBLIOGRAPHY .................................................................................................... 108 v LIST OF TABLES Table Page 4.1 Logical Effort for inputs of static CMOS gates .............................................. 42 4.2 Estimates of parasitic delay for logic gates..................................................... 44 4.3 Best Number of stages for path efforts............................................................ 49 4.4 Summary of terms and equations for Logical Effort....................................... 50 5.1 Selection Table for a Flagged Prefix Adder ................................................... 55 6.1 Flag and Carry Logic Based on Third Operand .............................................. 69 6.2 Flag Logic utilizing Carry from the Prefix Tree ............................................. 69 6.3 Minimum Flag Logic Gates ............................................................................ 73 6.4 Logic Gate Combinations................................................................................ 73 6.5 Gate Count for All Adder Implementations.................................................... 78 7.1 Logical Effort and Path Delays for Adder Blocks .......................................... 81 7.2 Logical Effort and Path Delays for Gates within Adder Blocks..................... 83 7.3 Logical Effort Estimates for Conventional Adder Designs ............................ 84 7.4 Logical Effort Estimates for Flagged Adder Designs ..................................... 85 7.5 Logical Effort Estimates for Three – Input Flagged Adder Designs .............. 87 7.6 Post – Layout Estimates for Conventional Adder Architectures .................... 94 7.7 Post – Layout Estimates for Flagged Adder Architectures............................. 94 7.8 Post – Layout Estimates for Enhanced Adder Architectures with Constant Addition ............................................................................................................ 95 7.9 Post – Layout Estimates for Three - Input Adder Architectures..................... 95 vi LIST OF FIGURES Figure Page 3.1 (m,k) Counter .................................................................................................. 19 3.2 Symbol and Logic for Half Adder................................................................... 20 3.3 Symbol and Logic for Full Adder ................................................................... 21 3.4 Ripple Carry Adder ......................................................................................... 22 3.5 m-bit Conditional Sum Adder......................................................................... 23 3.6 Carry-Select Adder.......................................................................................... 24 3.7 Carry-Skip Block ............................................................................................ 26 3.8 Carry-Skip Adder ............................................................................................ 26 3.9 Optimal Size for Carry-Skip Adder ................................................................ 29 3.10 Carry-Save Adder ........................................................................................... 29 3.11 Parallel Prefix Adder....................................................................................... 33 3.12 Logic and Symbol for Pre-Processing Gates .................................................. 34 3.13 Logic and Symbol for Prefix Tree Gates ........................................................ 34 3.14 Logic and Symbol for Post-Processing Gates................................................. 35 3.15 Brent-Kung Prefix Tree .................................................................................. 36 3.16 Ladner-Fischer Prefix Tree............................................................................. 37 3.17 Kogge-Stone Prefix Tree ...............................................................................