Embedded systems & the Nios II soft core processor A Nios II processor system I equivalent to a microcontroller or System on a chip (SoC) The Nios II processor family consits of two configurable 32-bit Harvard architecture cores Fast (/f core): Six-stage pipeline optimized for highest performance, optional memory management unit, or memory protection unit Economy (/e core): Optimized for smallest size, and available at no cost (no license required) • One-stage pipeline à one instruction per six clock cycles Choosing the core in Platform Designer NIOS–II Core block diagram • A general-purpose RISC processor core • 32-bit instruction set, data path, and address space • 32 general-purpose registers • Optional shadow register sets – useful for context switching on multitasking systems (e.g. Interrupts, RTOS) • 32 interrupt sources • External interrupt controller interface for more interrupt sources • Supports single-precision floating-point operations Nios II Processor Reference Guide, Intel, Available online: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/n2cpu-nii5v1gen2.pdf Nios II performance https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/ds_nios2_perf.pdf https://en.wikipedia.org/wiki/List_of_ARM_microarchitectures Nios II performance Compared to: ARM Cortex – M1 ARM Cortex - A9 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/ds_nios2_perf.pdf https://en.wikipedia.org/wiki/List_of_ARM_microarchitectures Nios II performance Example minimum implementation MAX 10 in chip planner NIOS II • A widely used soft processors in the FPGA industry – Soft core IP • Supports Intel’s (former Altera) FPGAs and is even available for standard-cell ASICs (Synopsys). • Access to a variety of on-chip peripherals and interfaces to off-chip memories and peripherals • Software development environment based on the GNU C/C++ tool chain and Eclipse IDE..