State of the Union Krste Asanovic UC Berkeley, RISC-V Foundation, & SiFive Inc. [email protected] 7th RISC-V Workshop Western DiGital, Milpitas, CA November 28, 2017 What is RISC-V? § A hiGh-quality, license-free, royalty-free RISC ISA specification oriGinally from UC Berkeley § Standard maintained By non-profit RISC-V Foundation § SuitaBle for all types of computinG system, microcontrollers to supercomputers § Numerous proprietary and open-source cores § ExperiencinG rapid uptake in industry and academia § Supported By GrowinG shared software ecosystem § A work in proGress… What’s Different about RISC-V? § Simple - Far smaller than other commercial ISAs § Clean-slate design - Clear separation Between user and privileged ISA - Avoids µarchitecture or technoloGy-dependent features § A modular ISA desiGned for extensibility/specialization - Small standard Base ISA, with multiple standard extensions - Sparse and variaBle-lenGth instruction encodinG for vast opcode space § Stable - Base and standard extensions are frozen - Additions via optional extensions, not new versions § Community designed - Developed with leading industry/academic experts and software developers 3 RISC-V Timeline PrivileGed Arch, v1.10 RISC-V Foundation Incorporated RV32E, RVC 1.9 PrivileGed Arch, v1.7, RVC v1.7 Hot Chips 2014 User ISA v2.0 IMAFD SoC 1st Rocket tapeout, EOS14, 45nm Softcores User ISA v1.0, You Raven-1 tapeout (28nm), are Workshop RVC MS thesis Workshop Commercial th First Linux st st here 7 RISC-V ISA project BeGins 1 Commercial 1 Berkeley World 4 Modest RISC-V Project Goal Become the industry-standard ISA for all computing devices So, how’s it going? 5 Industry Adoption Status § Large companies adoptinG RISC-V for deeply emBedded controllers in their SoCs (“minion cores”) - NVIDIA are puBlic with this, others in proGress privately - Replaces home-Grown and commercial cores § CTOs across entire value chain of IC suppliers, system providers, service providers, are aware and imagininG/evaluatinG strateGies to leverage RISC-V 6 Replacing 2nd-tier ISAs § Smaller proprietary-ISA soft-core IP companies switching to RISC-V standard to access larGer market: - Andes - Codasip - Cortus - others to announce If you’re a softcore IP provider, you should have a RISC-V product in development 7 Government Adoption § India has adopted RISC-V as national ISA § US DARPA mandated RISC-V in recent security call for proposals § Israel Innovation Authority creatinG genPro platform around RISC-V § Other countries at various staGes of investiGation If your country wishes to control security of its own information infrastructure, and further its own domestic semiconductor industry, sponsor RISC-V 8 Startups § Many startups choosing RISC-V for new products § Most are stealthy so will not be visible for at least another year We haven’t had to tell startups about RISC-V; they find out pretty quickly when shopping for processor IP 9 Commercial Ecosystem Providers § A theme at this workshop is mainstream commercial ecosystem support - Express LoGic, Imperas, Lauterbach, Micrium, SeGGer, UltraSOC, … Demand is driving supply in commercial ecosystem 10 RISC-V in Academic Research § BecominG standard ISA for academic research - Celerity >500 RISC-V core SoC in 16nm FinFET - FireSim modelinG 1,024 quad-core RISC-V servers in cloud § Recent “1st Workshop on Computer Architecture Research using RISC-V” (CARRV) at 50th MICRO in Boston was larGest workshop (standinG room only) – even Bigger than machine learning tutorial 11 RISC-V in Education Available December! Books available now! RISC-V spreading quickly throughout curricula of top schools 12 RISC-V: Completing the Innovation Cycle Research Open ecosystem is key to keepinG the virtuous cycle GoinG Industry Education 13 Foundation: 100+ Members 14 RISC-V Foundation RISC-V Foundation Growth History August 2015 to November 2017 100 80 60 40 20 0 Q3 2015 Q4 2015 Q1 2016 Q2 2016 Q3 2016 Q4 2016 Q1 2017 Q2 2017 Q3 2017 Q4 2017 Platinum Gold Silver Auditor Individual 15 Marketing Committee § Hired Racepoint GloBal as Foundation marketinG firm § MessaGing & MarketinG Kit released § Social Media proGram active - ReGular Twitter & LinkedIn updates § Multiple RISC-V events (outside the Foundation) - CARRV, SoC Conf Irvine, EEWorld weBinar § WeBsite refresh – RISC-V news aGGreGator § 7th Workshop has 15 editors/analysts in attendance 16 Upcoming Events § RISC-V Tokyo (Dec 18th, 2017) § EmBedded World - Have RISC-V booth and day long RISC-V series of talks § 8th RISC-V workshop May 2018 in Barcelona - Other reGional events BeinG considered § DAC June 2018 § HotChips August 2018 § Linley Processor Conference October 2018 § More to come… 17 RISC-V Technical Roadmap for 2017 § Primary Goals were to formally standardize Base ISA, memory model, deBuG, and staBilize privileGed architecture for Unix ports and tapeouts § Several corners/holes of Base ISA fixed, But not quite ratified due to spec versus profiles clarifications - No plans to chanGe any instruction specifications versus 2.0 § Unix platform staBle as of priv 1.10 - Only Backward-compatiBle chanGes thereafter 18 ISA Specifications and Profiles § OriGinal ISA specs mixed instruction specifications with platform mandates - But difficult to aGree Given wide ranGe of platforms (4KiB microcontroller versus 1TiB Unix server) § Now separatinG instruction set specifications from platform profiles - Maximize reuse of instruction set specifications for different use cases - Constrain profiles more tiGhtly to simplify software compatiBility 19 Expanded naming of instruction sets § SinGle-letter names will run out someday § Need finer-grain naming of instruction sets to describe profiles: - some C instructions depend on F or D BeinG present - how to report multiply not divide implemented? - need to specify potentially dozens of crypto extensions § Use Zxxxx to name standard instruction extensions (Xyyy used for non-standard instructions) § ExistinG sinGle-letter names retain meaninG § In active discussion on isa-dev mailinG list 20 Profiles for Software Compatibility § Software ABI/SBI defines a profile - What harts, reGisters, instructions, memory are available - How process/OS is started/terminated - How I/O happens - For Unix, ABI/SBI assumes IMAFDC=gC instructions § Need profiles for M-mode-only microcontrollers - For portable libraries in M-mode § and profiles for MU-mode microcontrollers - For each RTOS using M&U modes § and for BootinG MSU platforms § Instruction specs reused in all these profiles § Aim to have first ready in Q1 2018 21 Memory Model § Original model was too weak for C11 and also underspecified § AmazinG work By many experts over course of year § We have a resolution: - RVWMO is RISC-V Base ISA memory model, weakly ordered - detailed formal specs, both axiomatic and operational! - mapping from C11 to base ISA only, and with A extension - also defined RVTSO as optional extension providinG stronG TSO memory model (RVTSO strict suBset of RVWMO) - see Daniel LustiG’s talk later this morninG 22 ABI and Compilers § Calling convention and ABI has Been staBilized and documented § GCC and binutils have been upstreamed and released in GCC 7.1 (SiFive, Andes) § LLVM upstream in proGress (lowRISC, Andes) § Other compilers/lanGuages: CompCert, go, Rust, OCaml, Jikes JVM, OpenJDK (not JIT yet), Forth, Pascal,… 23 Unix Platform § PrivileGed Architecture 1.10 released at last workshop § Intent is for future additions to Be Backwards- compatiBle with 1.10 § Linux port accepted upstream for 4.15 release! § FreeBSD mainline since 11.0 § Hypervisor spec released - DesiGned to support recursive virtualization usinG enhanced S mode § See Andrew Waterman’s talk next 24 Other OS Ports § Many other OS ports in proGress or completed - FreeRTOS - ZephyrOS - Apache MyNewt - RIOT - seL4 - uC/OS - LiteOS - RTEMS - ThreadX - … 25 Run-Halt Debug § Successful collaBoration Between many orGanizations has resulted in a stable version awaiting ratification § Provides an aBstract interface to deBuG system to support alternative implementation styles § BeinG tarGeted By commercial ecosystem partners 26 Summary of 2017 Technical Roadmap § All planned major technical decisions settled § Some more work on ratification process needed 27 Technical Roadmap Goals for 2018 § Complete ratification of Base ISA and first profiles - IMADFC, deBuG specifications - Unix ABI/SBI profiles - M, MU, and MSU-mode platform profiles § Base vector extensions proposed and ratified - Validate with compiler support in LLVM, gcc § Hypervisor implemented, spec ratified - KVM primary, Beehive and Xen secondary § Formal spec completed and released 28 Vector Extensions § ReconfiGuraBle, vector-lenGth-aGnostic, mixed-precision, vector unit that replaces other ISAs’ packed-SIMD extensions § Ideal for machine learninG, DSP, Graphics, supercomputinG,… § ConsideraBle movement on desiGn, GettinG simpler § Support for scalar, 1D vector, and 2D matrix “shapes”of various types (floatinG, int, 8B, 16B, 32B, .., 512B) § Crypto extension Builds on wide scalar Bit vectors § “Best Vector ISA Ever” ™ § Talk tomorrow By RoGer Espasa 29 Security § Really two separaBle efforts in Foundation: - Trusted execution environments (TEE) - CryptoGraphic instruction extensions § Much other work includinG MIT Sanctum (enclaves), lowRISC (taGGed memory), CHERI (capaBilities), Dover (accelerated metadata rules), secure Boot (Microsemi, RamBus), … § RISC-V is dominatinG security research § Everyone aGrees security is really important § No industry aGreement on riGht