Product Order Technical Tools & Support & Folder Now Documents Software Community TMS320C6652, TMS320C6654 SPRS841E –MARCH 2012–REVISED OCTOBER 2019 TMS320C6652 and TMS320C6654 Fixed and Floating-Point Digital Signal Processor 1 Device Overview 1.1 Features 1 • One TMS320C66x DSP Core Subsystem – 32-Bit DDR3 Interface (CorePac) – DDR3-1066 – C66x Fixed- and Floating-Point CPU Core: Up – 4GB of Addressable Memory Space to 850 MHz for C6654 and 600 MHz for C6652 – 16-Bit EMIF • Multicore Shared Memory Controller (MSMC) – Universal Parallel Port – Memory Protection Unit for DDR3_EMIF – Two Channels of 8 Bits or 16 Bits Each • Multicore Navigator – Supports SDR and DDR Transfers – 8192 Multipurpose Hardware Queues with – Two UART Interfaces Queue Manager – Two Multichannel Buffered Serial Ports – Packet-Based DMA for Zero-Overhead (McBSPs) Transfers – I2C Interface • Peripherals – 32 GPIO Pins – PCIe Gen2 (C6654 Only) – SPI Interface – Single Port Supporting 1 or 2 Lanes – Semaphore Module – Supports up to 5 GBaud Per Lane – Eight 64-Bit Timers – Gigabit Ethernet (GbE) Subsystem (C6654 – Two On-Chip PLLs Only) • Commercial Temperature: – One SGMII Port (C6654 Only) – 0°C to 85°C – Supports 10-, 100-, and 1000-Mbps • Extended Temperature: Operation – –40°C to 100°C 1.2 Applications • Power Protection Systems • Medical Imaging • Avionics and Defense • Other Embedded Systems • Currency Inspection and Machine Vision • Industrial Transportation Systems 1.3 Description The C6654 and C6652 are high performance fixed- and floating-point DSPs that are based on TI's KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 850 MHz for C6654 and 600 MHz for C6652. For developers of a broad range of applications, both C6654 and C6652 DSPs enable a platform that is power-efficient and easy to use. In addition, the C6654 and C6652 DSPs are fully backward compatible with all existing C6000™ family of fixed- and floating-point DSPs. TI's KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMS320C6652, TMS320C6654 SPRS841E –MARCH 2012–REVISED OCTOBER 2019 www.ti.com For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating-point capability and the per-core raw computational performance is an industry-leading 27.2 GMACS per core and 13.6 GFLOPS per core (@850 MHz frequency). The C66x core can execute 8 single precision floating-point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating-point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backward code-compatible with TI's previous generation C6000 fixed- and floating-point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware. The C6654 and C6652 DSPs integrate a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at a rate of 1066 MHz and has ECC DRAM support. This family supports a number of high-speed standard interfaces including PCI Express Gen2 and Gigabit Ethernet (PCIe and Gigabit Ethernet are not supported on the C6652). This family of DSPs also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronous EMIF, along with general-purpose CMOS IO. The C6654 and C6652 devices have a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution. TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. The KeyStone architecture is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This internal bandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, and Multicore Shared Memory Controller. Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller lets processing cores access shared memory directly without drawing from the capacity of TeraNet, so packet movement cannot be blocked by memory access. Device Information(1) PART NUMBER PACKAGE BODY SIZE GZH (625) 21 mm × 21 mm TMS320C6652 CZH (625) 21 mm × 21 mm GZH (625) 21 mm × 21 mm TMS320C6654 CZH (625) 21 mm × 21 mm (1) For more information, see Section 11, Mechanical Packaging and Orderable Information. 2 Device Overview Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C6652 TMS320C6654 TMS320C6652, TMS320C6654 www.ti.com SPRS841E –MARCH 2012–REVISED OCTOBER 2019 1.4 Functional Block Diagram Figure 1-1 shows the functional block diagrams of the device. C6654 Memory Subsystem 32-Bit DDR3 EMIF MSMC Debug and Trace Boot ROM Semaphore Timers C66x CorePac Power Management 32KB L1 32KB L1 P-Cache D-Cache PLL ´2 1024KB L2 Cache EDMA 1 Core @ 850 MHz TeraNet Multicore Navigator Queue Packet Manager DMA 2 ´ ´ Ethernet ´ 2 MAC IC SPI UPP GPIO EMIF16 PCIe 2 UART 2 McBSP SGMII Copyright © 2016, Texas Instruments Incorporated (1) See Table 3-1 for feature difference between the C6654 and C6652 devices. Figure 1-1. C6654 and C6652 Functional Block Diagram Copyright © 2012–2019, Texas Instruments Incorporated Device Overview 3 Submit Documentation Feedback Product Folder Links: TMS320C6652 TMS320C6654 TMS320C6652, TMS320C6654 SPRS841E –MARCH 2012–REVISED OCTOBER 2019 www.ti.com Table of Contents 1 Device Overview ......................................... 1 6.16 Timers.............................................. 151 1.1 Features .............................................. 1 6.17 Semaphore2 ....................................... 151 1.2 Applications........................................... 1 6.18 Multichannel Buffered Serial Port (McBSP)........ 152 1.3 Description............................................ 1 6.19 Universal Parallel Port (uPP) ...................... 153 1.4 Functional Block Diagram ............................ 3 6.20 Emulation Features and Capability ................ 154 2 Revision History ........................................ 5 6.21 DSP Core Description ............................. 155 3 Device Comparison ..................................... 6 6.22 Memory Map Summary............................ 158 3.1 Device Comparison................................... 6 6.23 Boot Sequence .................................... 162 3.2 Related Products ..................................... 7 6.24 Boot Modes Supported and PLL Settings ......... 163 4 Terminal Configuration and Functions.............. 8 6.25 PLL Boot Configuration Settings................... 182 4.1 Pin Diagram .......................................... 8 6.26 Second-Level Bootloaders......................... 182 4.2 Terminal Functions.................................. 17 7 C66x CorePac.......................................... 183 5 Specifications ........................................... 41 7.1 Memory Architecture ............................... 184 5.1 Absolute Maximum Ratings ......................... 41 7.2 Memory Protection................................. 187 5.2 ESD Ratings ........................................ 41 7.3 Bandwidth Management ........................... 188 5.3 Recommended Operating Conditions............... 42 7.4 Power-Down Control............................... 188 5.4 Power Consumption Summary...................... 42 7.5 C66x CorePac Revision ........................... 189 5.5 Electrical Characteristics ............................ 43 7.6 C66x CorePac Register Descriptions.............. 189 5.6 Thermal Resistance Characteristics for