Preventing GaN Device VHF Oscillation APEC 2017 Zan Huang, Jason Cuadra APEC 2017 | 1 Parasitic oscillation • Parasitic oscillation can occur in any switching circuit with fast- changing voltage and current that stimulate a parasitic LC network • The oscillation becomes sustained when positive feedback with gain is present • The feedback could be through parasitic capacitance, parasitic inductance, shared or coupling inductance, etc. • Together with the device gain in the linear region, creates an oscillator • Preventing oscillation in fast-switching GaN devices is more challenging than in silicon due to • Faster dv/dt and di/dt • Higher transconductance • Violent sustained VHF oscillation (50-200MHz) will cause destruction APEC 2017 | 2 Sustained oscillation • In a half-bridge circuit with high speed devices on both the high and low side, there are three steps that yield sustained oscillation on the high-side device during low-side device turn-on, and vice versa Note: Sustained oscillation can occur even in a single-ended circuit, with very fast switching, e.g. a boost converter using a FET+diode; the analysis is similar to a half-bridge APEC 2017 | 3 Step 1: VGS change due to high dv/dt • During low-side turn-on, the high-side FET is subjected to a large positive dv/dt, which couples through CGD to increase VGS, (“Miller effect”) reducing its off-voltage margin against gate threshold VTH • To counter this, Transphorm devices are designed with a low ratio of CGD to CGS to minimize the Miller effect APEC 2017 | 4 Step 2: VGS change due to high di/dt Lpcb • During low-side turn on, the high-side FET sees a decreasing Ld current with a large negative di/dt, which multiplied by stray Rg Coss inductance LS in the PCB layout, V Vg_off gs - iL produces a voltage VLS , and also V Ls + Ls reduces the off-voltage margin Lrtn Cb Lf • It is necessary to have a tight Ld layout and minimize the stray Coss inductance Ls Lpcb APEC 2017 | 5 Step 3: Amplification due to transconductance • If VGS is pulled above the threshold voltage VTH, the device will operate in the linear region with transconductance gm, which can be defined in below equation: ID=(VGS-VTH)*gm • The large gain in the feedback loop that includes external stray capacitance Cgd_ext can then create a sustained oscillation APEC 2017 | 6 The feedback loop transfer function C gd_ext Ld1 Simplified Q1 D Vds_Q1 LDS = LD + LS L Cgd Rg1 FB1 g1 Vgs Cds CGD = CGD0 + CGD_EXT Cgs Vg_off G dVds/dt Cgd_ext S Ld Vgs Lg V Lds Vgs Lg Vds ds Vdc V Vds_int ds_int Cgd0 + Cgd + Vsw Ls1 Lf Cgs Cgs C LFB C LFB Gate Driver dVds/dt ds dVds/dt ds Ld2 I Ls RG RG D L - - Cgd Q2 Rg2 FB2 Lg2 Vgs Cds G Cgs Vgs_on S , Ls2 �%& � � �-.�0&& + ��%�0&& + 1 � � = = ��'& + 3 , �'&(�) � �-.(�0&&�45 + �65�64) + � �% �45�0&& + �65�64 + ��7&& + 1 Where: �0&& = �65 +�64, �7&& = �45 + �64, and Lds = Ld +LS APEC 2017 | 7 Comparing ringing amplitude RG_OFF=1Ω, CGD_EX =2pF RG_OFF=1Ω, CGD_EXT=2pF RG_OFF=1Ω, CGD_EXT=2pF Lead_length=15mm (7.5nH) Lead_length=10mm (5nH) Lead_length=5mm (2.5nH) Vgs_pk=8.1V, 5V Vgs_pk=7.5V, 5.2V Vgs_pk=6.5V, 4.5V § Comparing blue and red curves, higher dV/dt increases the amplitude of the VGS ringing Red : dVDS/dt=40V/ns § Comparing different parasitic inductances, higher Blue : dVDS/dt=100V/ns inductances increases the amplitude of the VGS ringing APEC 2017 | 8 To suppress the sustained oscillation • Required • Optimize PCB layout • Use a ferrite bead in the gate • Highly recommended • Add a ferrite bead to the drain • Improves efficiency because excessive ringing is lossy • Optional • Add negative Vg_off voltage • Reduce the turn-on dv/dt • Add an RC snubber to damp the ringing energy • Slightly reduces efficiency NOTE: The above can apply to a single-ended converter with very fast switching APEC 2017 | 9 Choosing a Drain Ferrite Bead APEC 2017 | 10 Example: Bridge circuit Lpcb Lpcb Ld Ld ESL Coss ESL Coss Ls Cd Ls FB FB Ld Ld Coss Ls Ls Lpcb Lpcb • The equivalent LC resonant loop that largely determines the power loop oscillation frequency L = 2*LD + 2*LS + ESL+ LPCB + LWIRE C = COSS, (one COSS is bypassed when device is conducting) APEC 2017 | 11 Adding the ferrite bead into the circuit ‘Ring’ (through-hole) type of the ferrite bead SMD type of ferrite bead should be placed on PCB can be placed on through-hole type device’s without interfering with the heat dissipation from the D pin large pad (drain for TPHxxxLD part, source for TPHxxxLS part) APEC 2017 | 12 Transphorm PQFN Package Variations APEC 2017 | 13 Choose a ferrite bead as a damping resistor at the ringing frequency (50-200MHz) inductance resistive capacitance region region region For a series LCR circuit, the damping factor is given by: > A ? � = , @ Choose the ferrite bead that R>X For critical damping, R should be: @50-200MHz, so the ferrite bead A � A 25�� shows more resistive than � = 2� = 2 ∗ 1 ∗ = 30Ω inductive in this region � 110�� So use a bead with >30Ω@100MHz for each device APEC 2017 | 14 Verifying the result Note the ringing Note the ringing is well damped APEC 2017 | 15 TPH3212 HB low side switching w/o FB Turn off at 20A, oscillate Turn off at 16A, Turn off at 18A, voltage spike damped voltage spike damped to <20% after 3 cycles: to >20% after 3 cycles: Stable Almost unstable APEC 2017 | 16 TPH3212 HB low side switching w/ FB Turn off at 20 and 24A, no ringing: Stable APEC 2017 | 17 VTDS rating • Using a drain ferrite bead does increase the drain spike voltage • However, all Transphorm devices are specified with VTDS (transient VDS) which is 150V higher than the rated max DC VDS • Transphorm devices are guaranteed to operate safely under repetitive spike voltages within the datasheet specification, making it more suitable for the drain ferrite bead solution APEC 2017 | 18 APEC 2017 | 19 Paralleling 650V/52mohm GaN with FB APEC 2017 | 20 Layout with TO247 Packages LS Q2,Q4 HS Q1,Q3 APEC 2017 | 21 Switching 400V/100A with Clean Waveform APEC 2017 | 22 200V:400V Boost Converter 5.5kW and 98.8% Peak Efficiency 99 140 120 98 100 80 97 60 Efficiency (%) 40 96 20 95 0 0 1000 2000 3000 4000 5000 6000 Power (W) Efficiency w/o RC snubber Ploss w/o RC snubber APEC 2017 | 23 Silicon Valley Center of Excellence Design Tools: Evaluation Support: Global field applications kits, reference designs, team, Q+R testing, system simulation models (SPICE) component selection analysis, technical marketing 150 Years of GaN Experience magnetics, noise control, PCB design, Q+R testing, tools, etc. Education: EMI control Technical Library: Application methods, high power app notes, design guides, PCB layouts, concepts, optimization schematics, technical white techniques, topology papers comparisons, etc. APEC 2017 | 24 Thank You! APEC 2017 | 25.