See all versions of this document UltraFast Design Methodology Guide for the Vivado Design Suite UG949 (v2019.2) December 6, 2019 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 12/06/2019 Version 2019.2 Thermal Solution Considerations Added new section. Performance/Power Trade-Off for Block RAMs Updated examples. Using the CLOCK_LOW_FANOUT Constraint Updated examples. Using Incremental Implementation Flows Added information about automatic incremental implementation mode. Incremental Directives and Target WNS Added new section. Compile Time Considerations Added new section. Assessing the Maximum Frequency of the Design Added new section. Reducing Clock Delay in UltraScale and UltraScale+ Devices Added new section. Disable LUT Combining Updated example. ML Strategies Added new section. Using Incremental Implementation Added information about automatic incremental implementation mode. Using VIO Cores Added new section. 06/26/2019 Version 2019.1 About the UltraFast Design Methodology Added reference to UltraFast Design Methodology Timing Closure Quick Reference Guide (UG1292). SLR Utilization Considerations Updated example. Auto-Pipelining Considerations Added new section. Using Auto-Pipelining on Custom Interfaces Updated to show the hierarchy recommendation and USER_SLR_ASSIGNMENT constraints. Synchronous CDC Added note about safe timing between BUFGCE_DIV clocks. Incremental Synthesis Flows Added new section. Using Incremental Implementation Flows Added information on automatic incremental implementation. Optimization Analysis Added -debug_log option. Methodology DRCs with Impact on Timing Closure Added Severity column and TIMING-44 and TIMING-45 checks. Methodology DRCs with Impact on Signoff Quality Added Severity column and TIMING-46 check. Optimizing Paths with Dedicated Blocks and Macro Added optimization options. Primitives Interconnect Congestion Level in the Device Window Added enhanced reporting information. Choose a High Quality Reference Checkpoint Added information on selecting different timing closed checkpoints and using incremental synthesis. Considering Floorplan Added tip about IS_SOFT property. Using Hard SLR Floorplan Constraints Added tip about IS_SOFT property. UG949 (v2019.2) December 6, 2019Send Feedback www.xilinx.com UltraFast Design Methodology Guide 2 Revision History Section Revision Summary Using Soft SLR Floorplan Constraints Updated XDC constraint example for optimal placement. Using SLR Crossing Registers Added USER_SLL_REG property. Using Auto-Pipelining for SLR Crossings Added new section. UG949 (v2019.2) December 6, 2019Send Feedback www.xilinx.com UltraFast Design Methodology Guide 3 Table of Contents Revision History...............................................................................................................2 Chapter 1: Introduction............................................................................................. 6 About the UltraFast Design Methodology................................................................................6 Understanding UltraFast Design Methodology Concepts..................................................... 9 Using the Vivado Design Suite.................................................................................................12 Accessing Additional Documentation and Training..............................................................13 Chapter 2: Board and Device Planning............................................................. 14 PCB Layout Recommendations............................................................................................... 14 Clock Resource Planning and Assignment.............................................................................19 I/O Planning Design Flows.......................................................................................................20 Designing with SSI Devices...................................................................................................... 26 Designing with HBM Devices...................................................................................................32 Device Power Aspects and System Dependencies................................................................36 Configuration.............................................................................................................................39 Chapter 3: Design Creation..................................................................................... 41 Design Creation with RTL......................................................................................................... 41 Working with Constraints.......................................................................................................144 Chapter 4: Implementation.................................................................................. 183 Running Synthesis...................................................................................................................183 Moving Past Synthesis............................................................................................................187 Implementing the Design...................................................................................................... 191 Chapter 5: Design Closure......................................................................................200 Timing Closure.........................................................................................................................200 Power Analysis and Optimization......................................................................................... 281 Configuration and Debug...................................................................................................... 284 Appendix A: Additional Resources and Legal Notices........................... 295 Xilinx Resources.......................................................................................................................295 UG949 (v2019.2) December 6, 2019Send Feedback www.xilinx.com UltraFast Design Methodology Guide 4 Solution Centers...................................................................................................................... 295 Documentation Navigator and Design Hubs...................................................................... 295 References................................................................................................................................296 Training Resources..................................................................................................................298 Please Read: Important Legal Notices................................................................................. 299 UG949 (v2019.2) December 6, 2019Send Feedback www.xilinx.com UltraFast Design Methodology Guide 5 Chapter 1: Introduction Chapter 1 Introduction About the UltraFast Design Methodology The Xilinx® UltraFast™ design methodology is a set of best practices intended to help streamline the design process for today's devices. The size and complexity of these designs require specific steps and design tasks to ensure success at each stage of the design. Following these steps and adhering to the best practices will help you achieve your desired design goals as quickly and efficiently as possible. Xilinx provides the following resources to help you take advantage of the UltraFast design methodology: • This guide, which describes the various design tasks, analysis and reporting features, and best practices for design creation and closure. • UltraFast Design Methodology Quick Reference Guide (UG1231), which highlights key design methodology steps in an easy-to-use, double-sided card format. • UltraFast Design Methodology Timing Closure Quick Reference Guide (UG1292), which covers recommendations for closing timing, including running initial design checks, baselining the design, and resolving timing violations. • UltraFast Design Methodology Checklist (XTP301), which is available in the Xilinx Documentation Navigator and as a standalone spreadsheet. You can use this checklist to identify common mistakes and decision points throughout the design process. • UltraFast Design Methodology System-Level Design Flow diagram representing the entire Vivado® Design Suite design flow, which is available in the Xilinx Documentation Navigator. You can click a design step in the diagram to open related documentation, collateral, and FAQs to help get you started. RECOMMENDED: In addition to these resources, Xilinx recommends the UltraFast Embedded Design Methodology Guide (UG1046) when working with embedded designs and the UltraFast High-Level Productivity Design Methodology Guide (UG1197) when developing complex systems using Vivado IP integrator with C- based IP. TIP: Xilinx also provides methodology-related design rule checks (DRCs) for each design stage, which are available using the report_methodology Tcl command in the Vivado Design Suite. UG949 (v2019.2) December 6, 2019Send Feedback www.xilinx.com UltraFast Design Methodology Guide 6 Chapter 1: Introduction Using This Guide This guide provides a set of best practices that maximize productivity for both system integration and design implementation. It includes high-level information, design guidelines, and design decision trade-offs for the following topics: • Board and Device Planning: Covers decisions and design tasks that Xilinx recommends accomplishing prior to design creation. These