<p>University of Pennsylvania </p><p><a href="/goto?url=https://repository.upenn.edu/" target="_blank">ScholarlyCommons </a></p><p><a href="/goto?url=https://repository.upenn.edu/cis_reports" target="_blank">Technical Reports (CIS) </a></p><p>December 1968 </p><p><a href="/goto?url=https://repository.upenn.edu/cis" target="_blank">Department of Computer &amp; Information Science </a></p><p>On-Line Computing With a Hierarchy of Processors </p><p>Richard P. Morton </p><p>University of Pennsylvania </p><p>Follow this and additional works at: <a href="/goto?url=https://repository.upenn.edu/cis_reports?utm_source=repository.upenn.edu%2Fcis_reports%2F804&amp;utm_medium=PDF&amp;utm_campaign=PDFCoverPages" target="_blank">https:</a><a href="/goto?url=https://repository.upenn.edu/cis_reports?utm_source=repository.upenn.edu%2Fcis_reports%2F804&amp;utm_medium=PDF&amp;utm_campaign=PDFCoverPages" target="_blank">/</a><a href="/goto?url=https://repository.upenn.edu/cis_reports?utm_source=repository.upenn.edu%2Fcis_reports%2F804&amp;utm_medium=PDF&amp;utm_campaign=PDFCoverPages" target="_blank">/</a><a href="/goto?url=https://repository.upenn.edu/cis_reports?utm_source=repository.upenn.edu%2Fcis_reports%2F804&amp;utm_medium=PDF&amp;utm_campaign=PDFCoverPages" target="_blank">repository.upenn.edu/cis_reports </a></p><p>Recommended Citation </p><p>Richard P. Morton, "On-Line Computing With a Hierarchy of Processors", . December 1968. </p><p>University of Pennsylvania Department of Computer and Information Science Technical Report No. MS-CIS-69-13. </p><p>This paper is posted at ScholarlyCommons. <a href="/goto?url=https://repository.upenn.edu/cis_reports/804" target="_blank">https:</a><a href="/goto?url=https://repository.upenn.edu/cis_reports/804" target="_blank">/</a><a href="/goto?url=https://repository.upenn.edu/cis_reports/804" target="_blank">/</a><a href="/goto?url=https://repository.upenn.edu/cis_reports/804" target="_blank">repository.upenn.edu/cis_reports/804 </a></p><p>For more information, please contact <a href="mailto:[email protected]" target="_blank">[email protected]</a>. </p><p>On-Line Computing With a Hierarchy of Processors </p><p>Abstract </p><p>Time shared computer systems have been based upon the two techniques of multiprogramming and swapping. Multiprogramming is based on restricting each program to a portion of the total computer memory. Swapping requires considerable overhead time for loading and unloading programs. To alleviate the size restriction due to multiprogramming, segmentation is employed, resulting in fact in vastly increased swapping. </p><p>A new system architecture is proposed for time shared computing that alleviates the high overhead or program size restriction. It utilizes a hierarchy of processors, where each processor is assigned tasks on the basis of four factors: interactive requirements, frequency of use, execution time, and program length. </p><p>In order to study the hierarchical approach to system architecture, the Moore School Problem Solving Facility (MSPSF) was built and used. The study of the manner of operation and the reactions of the users clarified and defined the Hierarchy of Processors system architecture. </p><p>The Moore School Problem Solving Facility was implemented on second generation equipment, the IBM 7040, and therefore it is not possible to adequately compare the efficiency with third generation computers operating in a swapping mode. The conclusions of this dissertation center around the methodology of designing such a system, including the specification of facilities for each level of the hierarchy. </p><p>Six major conclusions are given: (1) Three processors in the hierarchy have been necessary, but it is conceivable that more may be employed in other future situations. </p><p>(2) Each of the processors in the hierarchy should be general purpose. (3) Program compatibility between the processors is necessary. (4) The assigning of tasks to the processors within the system should be optionally user directed or automatic. Similarly, if a task exceeds the resources of the processor to which it has been assigned, redirection should be possible either automatically or by the user. </p><p>(5) A macro language is necessary between every pair of processors for effective communication. Such a language processor, IXSYS, has been constructed and its use is described in detail in the dissertation, demonstrating the need and utility. </p><p>(6) In addition to the three hierarchical processors, a separate processor may be advantageously used for storage, retrieval and management of information in files. Such a processor should be directly accessible from each of the other processors. </p><p>Comments </p><p>University of Pennsylvania Department of Computer and Information Science Technical Report No. MS- CIS-69-13. </p><p>This technical report is available at ScholarlyCommons: <a href="/goto?url=https://repository.upenn.edu/cis_reports/804" target="_blank">https:</a><a href="/goto?url=https://repository.upenn.edu/cis_reports/804" target="_blank">/</a><a href="/goto?url=https://repository.upenn.edu/cis_reports/804" target="_blank">/</a><a href="/goto?url=https://repository.upenn.edu/cis_reports/804" target="_blank">repository.upenn.edu/cis_reports/804 </a></p>