EE105 – Fall 2014 Microelectronic Devices and Circuits Prof. Ming C. Wu [email protected] 511 Sutardja Dai Hall (SDH) Lecture 9: MOSFET (2): Scaling, DC bias 1 NMOS Transistor Capacitances: Saturation Region • Drain no longer connected to channel 2 C = C +C W C = C W GS 3 GC GSO GD GDO Lecture 9: MOSFET (2): Scaling, DC bias 2 1 SPICE Model for NMOS Transistor Typical default values used by SPICE: 2 KP = 50 or 20 µA/V γ = 0 λ = 0 VTO = 1 V 2 µn or µp = 500 or 200 cm /V-s 2ΦF = 0.6 V CGDO = CGSO = CGBO = CJSW = 0 Tox= 100 nm Lecture 9: MOSFET (2): Scaling, DC bias 3 MOS Transistor Scaling • All physical dimensions shrinks by a factor of α • All voltages (including threshold voltage) reduced by α also – Constant field scaling • Drain current: * εox W α " vGS VTN vDS % vDS iD iD = µn $ − − ' = Tox α L α # α α 2α & 2α α * !W $! L $ C • Gate Capacitance: * " * * εox GC CGC = (Cox ) W L = # &# & = Tox α " α %"α % α • Circuit delay in a logic circuit. * * * ΔV CGC ΔV /α τ τ = CGC * = = iD α iD /α α Lecture 9: MOSFET (2): Scaling, DC bias 4 2 MOS Transistor Scaling Scale Factor α (cont.) • Circuit and Power Densities: V i P P* = V * i* = DD D = DD D α α α 2 P* P* P α 2 P = = = extremely important result! A* W *L* W L A ( α)( α) • Power-Delay Product: P τ PDP PDP* P* * € = τ = 2 = 3 α α α • Cutoff Frequency: gm µn € ω = = V −V T C L2 ( GS TN ) GC – fT improves with square of channel length reduction € Lecture 9: MOSFET (2): Scaling, DC bias 5 Impact of Velocity Saturation • At low electric field, electron velocity is proportional to field • At high electric field, the velocity reaches a maximum called saturation velocity, vSAT " CoxW iD = (vGS −VTN )vSAT 2 • The drain current is proportional to (vGS – VTN) rather than its square • There are (many) other corrections to the basic model when the channel become very short – Interested, take EE130 Lecture 9: MOSFET (2): Scaling, DC bias 6 3 NMOSFET in OFF State • We had previously assumed that there is no channel current when vGS < VTN. This is incorrect! • As vGS is reduced (toward 0 V) below VTN, the potential barrier to carrier diffusion from the source into the channel is increased. • The drain current ID is limited by carrier diffusion into the channel, rather than by carrier drift through the channel. • This is similar to the case of a PN junction diode! – ID varies exponentially with the potential barrier height at the source, which varies directly with the channel potential. Lecture 9: MOSFET (2): Scaling, DC bias 7 Sub-Threshold Leakage Current • In the depletion (sub-threshold) region of operation, the channel potential is capacitively coupled to the gate potential. A change in gate voltage (ΔvGS) results in a change in channel voltage (ΔvCS): # & ΔVCS iD ∝ exp% ( Similar to pn junction diode! $ VT ' # & Cox Cdep ΔVCS = ΔVGS ×% ( ≡ ΔVGS / m, m =1+ >1 $Cox +Cdep ' Cox Sub-threshold slope (also called sub-threshold swing): −1 # d(log I )& S ≡ % 10 DS ( $ dVGS ' S = mVT ln(10) > 60mV/dec Lecture 9: MOSFET (2): Scaling, DC bias 8 4 MOS Transistor Scaling (cont.) VDD Fixed Subthreshold • Sub-threshold Conduction: Slope – iD decreases exponentially for ON state vGS < VTN. current – Reciprocal of the slope in mV/decade gives the turn-off rate for the MOSFET. – Fundamental limit of MOSFET sub-threshold slope: 60mV/decade Leakage current Lecture 9: MOSFET (2): Scaling, DC bias 9 Mask Sequence Polysilicon-Gate Transistor • Mask 1: Defines active area or thin oxide region of transistor • Mask 2: Defines polysilicon gate of transistor, aligns to mask 1 • Mask 3: Delineates the contact window, aligns to mask 2. • Mask 4: Delineates the metal pattern, aligns to mask 3. • Channel region of transistor formed by intersection of first two mask layers. Source and Drain regions formed wherever mask 1 is not covered by mask 2 Lecture 9: MOSFET (2): Scaling, DC bias 10 5 Basic Ground Rules for Layout • Design of large circuits can be simplified with simple rules • Minimum feature size: F = 2 Λ • Minimum alignment between different features: T = Λ • Λ could be 1, 0.5, 0.25 µm, etc. • In this example: – W/L = 10Λ / 2Λ = 5 – Transistor Area = 120 Λ2 Lecture 9: MOSFET (2): Scaling, DC bias 11 MOSFET Biasing • ‘Bias’ sets the dc operating point. • The ‘signal’ is actually comprised of relatively small changes in the voltages and/or currents. • Remember (Total = dc + signal): vGS = VGS + vgs and iD = ID + id Lecture 9: MOSFET (2): Scaling, DC bias 12 6 Bias Analysis - Example 1: Constant Gate-Source Voltage Biasing VDD = ID RD +VDS V =10V − 50µA 100K = 5.00 V DS ( )( ) • Check:VDS > VGS-VTN. Hence € saturation region assumption is correct. Since IG = 0, VEQ = IG REQ +VGS = VGS • Q-pt: (50.0 mA, 5.00 V) with V = 3.00 V K 2 GS I = n V −V D 2 ( GS TN ) • Discussion: The Q-point of −6 25x10 A 2 2 this circuit is quite sensitive ID = 2 (3 −1) V = 50.0 µA 2 V to changes in transistor characteristics, so it is not widely used. € Lecture 9: MOSFET (2): Scaling, DC bias 13 Bias Analysis Using Load Line VDD = ID RD +VDS 10 105 I V = D + DS For VDS = 0, ID = 100 uA Check: The load line approach agrees For I = 0, V = 10 V D DS with previous calculation. € Plotting the line on the transistor Q-pt: (50.0 mA, 5.00 V) with VGS = 3.00 V output characteristic yields Q-pt at Discussion: Q-pt is clearly in the intersection with VGS = 3V device saturation region. Graphical load line is curve. good visual aid to see device operating region. Lecture 9: MOSFET (2): Scaling, DC bias 14 7 Bias Analysis - Constant Gate-Source Voltage Biasing with Channel-Length Modulation K 2 I = n V −V 1+ λV D 2 ( GS TN ) ( DS ) VDS = VDD − ID RD −6 25x10 2 V =10 − 105 3 −1 1+ 0.02V DS 2 ( )( ) ( DS ) VDS = 4.55 V −6 25x10 2 I 3 1 1 0.02 4.55 54.5 A D = ( − ) [ + ( )] = µ 2 Check: VDS > VGS - VTN. Hence the Discussion: The bias levels have € saturation region assumption is changed by about 10% (54.5 µA correct. vs 50 µA). Typically, component values will vary more than this, Q-pt: (54.5 mA, 4.55 V) with so there is little value in V = 3.00 V GS including λ effects in most circuits. Lecture 9: MOSFET (2): Scaling, DC bias 15 Bias Analysis - Example 6: Two-Resistor Feedback Biasing K 2 V = V − n V −V R GS DD 2 ( GS TN ) D −4 2.6x10 2 V = 3.3 − 104 V −1 GS 2 ( )( GS ) V = −0.769 V or + 2.00 V GS Since VGS < VTN for VGS = -0.769 V, the MOSFET would be cut-off, € V 2.00 V and I 130 A ∴ GS = + D = µ Assumption: IG = IB = 0, transistor is saturated (since V = V ) DS GS VDS > VGS-VTN. Hence saturation Analysis: V = V - I R region assumption is correct. DS DD D D € Q-pt: (130 µA, 2.00 V) Lecture 9: MOSFET (2): Scaling, DC bias 16 8 Bias Analysis - Example 6: Two-Resistor Feedback Biasing K 2 V = V − n V −V R GS DD 2 ( GS TN ) D −4 2.6x10 2 V = 3.3 − 104 V −1 GS 2 ( )( GS ) V = −0.769 V or + 2.00 V GS Since VGS < VTN for VGS = -0.769 V, the MOSFET would be cut-off, € V 2.00 V and I 130 A ∴ GS = + D = µ Assumption: IG = IB = 0, transistor is saturated (since VDS = VGS ) VDS > VGS-VTN. Hence saturation Analysis: VDS = VDD - IDRD region assumption is correct. € Q-pt: (130 µA, 2.00 V) Lecture 9: MOSFET (2): Scaling, DC bias 17 Bias Analysis – Two-Resistor biasing for PMOS Transistor Assumption: IG = IB = 0; transistor is saturated Analysis: VGS − IG RG −VDS = 0 → VDS = VGS VDD +VDS − ID RD = 0 Kn 2 VDD +VGS − (VGS −VTP ) RD = 0 2 −5 5 5x10 2 15+VGS − 2.2x10 (VGS + 2) = 0 ( ) 2 VGS = −0.369 V or − 3.45 V V > V V DS GS − TP Since VGS = −0.369 > VTP, VGS = −3.45 V Hence saturation assumption is € correct. ID = 52.5 µA and VDS = −3.45 V Q-pt: (52.5 µA, -3.45 V) € Lecture 9: MOSFET (2): Scaling, DC bias 18 9 .