Dv/dt-control methods for the SiC JFET/ Si MOSFET cascode . Daniel Aggeler, Member, IEEE, Francisco Canales, Member, IEEE, Juergen Biela, Member, IEEE, and Johann W. Kolar, Senior Member, IEEE „This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of ETH Zürich’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promo- tional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document you agree to all provisions of the copyright laws protecting it.” 4074 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013 Dv/Dt-Control Methods for the SiC JFET/Si MOSFET Cascode Daniel Aggeler, Member, IEEE, Francisco Canales, Member, IEEE, Juergen Biela, Member, IEEE, and Johann W. Kolar, Fellow, IEEE Abstract—Switching devices based on SiC offer outstanding per- formance with respect to operating frequency, junction tempera- ture, and conduction losses enabling significant improvement of the performance of converter systems. There, the cascode consist- ing of a MOSFET and a JFET has additionally the advantage of being a normally off device and offering a simple control via the gate of the MOSFET. Without dv/dt-control, however, the tran- sients for hard commutation reach values of up to 45kV/μs, which could lead to electromagnetic interference problems. Especially in drive systems, problems could occur, which are related to earth currents (bearing currents) due to parasitic capacitances. There- fore, new dv/dt-control methods for the SiC JFET/Si MOSFET cascode as well as measurement results are presented in this pa- per.Based on this new concepts, the outstanding performance of the SiC devices can be fully utilized without impairing electromagnetic Fig. 1. Switching behavior of the SiC-Si MOSFET (IRLR024N)/JFET cas- compatibility. code at Vdc = 800 V/ iD,C = 9A/11A. Proper hard switching behavior at turn ON and turn OFF event. Index Terms—dv/dt-control methods, SiC JFET, SiC-Si cascode. For voltages up to 600V, high performance MOSFET I. INTRODUCTION switches (e.g., COOLMOS) capable of working at high switch- HE trend for the design of power electronic systems ap- ing frequency with low switching losses are used in power fac- T plied for example in telecom applications is toward higher tor correction converter systems (e.g., VIENNA rectifier [2], [3]). power density and higher efficiency values. In order to reduce However, these devices offer a poor performance with respect to the system volume and achieve a higher power density, first conduction losses in the 1200 V range, so that usually insulated- the appropriate topology for the intended application must be gate bipolar transistors (IGBTs) are used, which have signifi- chosen. Second, the design parameters must be selected so that cantly higher switching losses. This limits the required operating minimal volume and/or higher efficiency result. Due to the large frequency in this voltage range and therewith also the achievable number of design parameters and coupling among them, it is ad- power density. In order to overcome this limitation, maturing de- vantageous to use an optimization procedure as presented in [1]. vices based on wide bandgap semiconductor materials such as There, a high switching frequency is usually required for min- SiC could be used. imizing the volume of the passive components. Furthermore, The SiC JFET [4] from SiCED/Infineon offers very fast switching losses of the semiconductors must be low for achiev- switching with transients up to 45 kV/μs (see Fig. 1) with a ing a high efficiency. blocking voltage of 1200 V due to its optimized vertical JFET structure with lateral channel [5]. However, the normally ON behavior of the SiC JFET prevents that the switch is fully ac- cepted for industry applications, in particular for voltage source converters (in current source pulse width modulation converter Manuscript received May 28, 2012; revised September 25, 2012; accepted normally ON devices are preferable), although improved gate November 13, 2012. Date of current version January 18, 2013. Recommended for publication by Associate Editor H.-P. (Guest EIC-Wide Bandgap) Nee. drive circuits have been developed [6]–[10]. D. Aggeler was with the Power Electronic Systems Laboratory, ETH A normally OFF behavior could be achieved by using a cas- Zurich, Zurich 8092, Switzerland. He is now with the ABB Switzer- code configuration with a low-voltage Si MOSFET in series land Corporate Research Center, Baden-Daettwil 5405, Switzerland (e-mail: [email protected]). with the 1200V SiC JFET as shown in Fig. 2, without losing F. Canales is with the ABB Switzerland Corporate Research Center, the excellent characteristics of the SiC device. In this config- Baden-Daettwil 5405, Switzerland (e-mail: [email protected]). uration, only the low-voltage MOSFET is actively controlled J. Biela is with the Laboratory for High Power Electronic Systems, ETH Zurich, Zurich 8092, Switzerland (e-mail: [email protected]). whereas the SiC JFET is inherently controlled by the drain– J. W. Kolar is with the Power Electronic Systems Laboratory, ETH Zurich, source voltage of the MOSFET. The gate drive circuit for the Zurich 8092, Switzerland (e-mail: [email protected]). SiC-Si cascode is a standard IGBT/MOSFET driver and there- Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. fore the currently used Si switches could directly be replaced Digital Object Identifier 10.1109/TPEL.2012.2230536 by the SiC JFET/Si MOSFET cascode. 0885-8993/$31.00 © 2012 IEEE AGGELER et al.:Dv/Dt-CONTROL METHODS FOR THE SiC JFET/Si MOSFET CASCODE 4075 Fig. 2. Cascode configuration and the two typical states of the SiC-Si cascode: (a) cascode switch topology, (b) the conduction mode (VGS,M >Vth,M ,where Fig. 3. Often used dv/dt limitation methods for MOSFET and IGBT switches. VGS,M is the MOSFET gate–source voltage and Vth,M denotes the threshold (a) Varying gate resistors and two- or three-step controlled gate voltage. voltage), and (c) the blocking mode (VGS,M <V ). th,M (b) Additional drain–source capacitor CDGa,M causes an increased negative miller feedback. As a result of high di/dt-values of 450 A/μs, which are tronically controlled and at the same time the optimal point for achieved with the SiC-Si cascode in hard commutated switch- minimal switching losses is calculated. ing actions as shown in Fig. 1, the effort for the design of a Most of these dv/dt limitation methods are based on the Miller low inductive layout avoiding switching related overvoltages Effect, 1+G [cf. (2)], which describes a capacitive feedback is mandatory. In [11], it was pointed out that overvoltages are M between the output and the input, e.g., of a MOSFET M device occurring due to parasitic and not avoidable module and layout inductances. Furthermore, the desire for a controllable dv/dt of d(vDS,M ) GM = − . (1) the cascode switching transients is also high to minimize elec- d(vGS,M ) tromagnetic interference (EMI) filtering effort [12], [13] and Therefore, the total equivalent input capacitance C seen to reduce conduction and emission aspects in certain applica- iss(eq) from the gate–source junction during the ON/OFF transition tions [14] and [15]. In [16], techniques are published for actively results in [17] control the dv/dt behavior of MOSFET devices to reduce voltage dv overshoots without requiring bulky and lossy snubber circuits. i =(C +(1+G ) · C ) · GS,M In this paper, novel methods to control and adjust the dv/dt- G,M GS,M M DG,M dt behavior of the SiC JFET/Si MOSFET cascode are presented. dv = C · GS,M . (2) First, standard and well-known control techniques for MOSFET iss(eq) dt and IGBT semiconductors are shortly discussed in Section II. Applying the conventional dv/dt-control techniques to the Second, the application of the conventional techniques con- SiC-Si cascode does not result in the desired control behavior trolling dv/dt is evaluated related to the cascode configuration. of reducing the fast switching voltages edges. The reason is Moreover, the novel dv/dt-controlling methods are described in the series connection of the low-voltage MOSFET and the SiC detail in Section III. Section IV presents experimental results JFET. The conventional methods only influence the behavior of of fast and controlled transients voltage edges of the cascode. the active controlled low-voltage MOSFET which is analyzed Finally, the switching energy losses of the SiC-Si cascode are and explained in the following. analyzed and conclusions are drawn. A. SiC-Si Cascode ONVENTIONAL Dv Dt IMITATION ECHNIQUES II. C / -L T To investigate the influence of the conventional dv/dt-control For state-of-the-art semiconductors as Si MOSFET and IGBT methods on the SiC-Si cascode configuration, a simulation setup devices, several techniques [14] to reduce and control the dv/dt (cf. schematic of experimental setup in Fig. 8) with LT SP ICE at fast switching edges are well known as shown in Fig. 3. The is elaborated. Here, standard SPICE models as supplied by the most simple and most frequently applied one is the control of manufacturers are used for the low-voltage MOSFETs [18] and the dv/dt with an external gate resistor RG,M , where the optimal the freewheeling SiC diode [19]. The applied SiC JFET model is gate resistance is selected based on the corresponding switching proposed in [20] where also the Spice parameters of a SiC JFET device.