Embedded Memories for Nano-Scale VLSIs Series on Integrated Circuits and Systems Series Editor: Anantha Chandrakasan Massachusetts Institute of Technology Cambridge, Massachusetts Embedded Memories for Nano-Scale VLSIs Kevin Zhang (Ed.) ISBN 978-0-387-88496-7 Carbon Nanotube Electronics Ali Javey and Jing Kong (Eds.) ISBN 978-0-387-36833-7 Wafer Level 3-D ICs Process Technology Chuan Seng Tan, Ronald J. Gutmann, and L. Rafael Reif (Eds.) ISBN 978-0-387-76532-7 Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice Alice Wang and Samuel Naffziger (Eds.) ISBN 978-0-387-76471-9 mm-Wave Silicon Technology: 60 GHz and Beyond Ali M. Niknejad and Hossein Hashemi (Eds.) ISBN 978-0-387-76558-7 Ultra Wideband: Circuits, Transceivers, and Systems Ranjit Gharpurey and Peter Kinget (Eds.) ISBN 978-0-387-37238-9 Creating Assertion-Based IP Harry D. Foster and Adam C. Krolnik ISBN 978-0-387-36641-8 Design for Manufacturability and Statistical Design: A Constructive Approach Michael Orshansky, Sani R. Nassif, and Duane Boning ISBN 978-0-387-30928-6 Low Power Methodology Manual: For System-on-Chip Design Michael Keating, David Flynn, Rob Aitken, Alan Gibbons, and Kaijian Shi ISBN 978-0-387-71818-7 Modern Circuit Placement: Best Practices and Results Gi-Joon Nam and Jason Cong ISBN 978-0-387-36837-5 CMOS Biotechnology Hakho Lee, Donhee Ham and Robert M. Westervelt ISBN 978-0-387-36836-8 Continued after index Kevin Zhang Editor Embedded Memories for Nano-Scale VLSIs 123 Editor Kevin Zhang Intel Corporation 2501 NW. 229th Ave. Hillsboro, OR 97124 USA [email protected] ISBN 978-0-387-88496-7 e-ISBN 978-0-387-88497-4 DOI 10.1007/978-0-387-88497-4 Library of Congress Control Number: 2008936472 c Springer Science+Business Media, LLC 2009 All rights reserved. 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Printed on acid-free paper springer.com Contents 1 Introduction .................................................... 1 Kevin Zhang 2 Embedded Memory Architecture for Low-Power Application Processor ....................................................... 7 Hoi Jun Yoo and Donghyun Kim 3 Embedded SRAM Design in Nanometer-Scale Technologies .......... 39 Hiroyuki Yamauchi 4 Ultra Low Voltage SRAM Design ................................. 89 Naveen Verma and Anantha P. Chandrakasan 5 Embedded DRAM in Nano-scale Technologies ......................127 John Barth 6 Embedded Flash Memory ........................................177 Hideto Hidaka 7 Embedded Magnetic RAM .......................................241 Hideto Hidaka 8 FeRAM ........................................................279 Shoichiro Kawashima and Jeffrey S. Cross 9 Statistical Blockade: Estimating Rare Event Statistics for Memories . 329 Amith Singhee and Rob A. Rutenbar Index .............................................................383 v Contributors John Barth IBM, Essex Junction, Vermont, [email protected] Anantha P. Chandrakasan Massachusetts Institute of Technology Cambridge, MA, USA Jeffrey S. Cross Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550, Japan, [email protected] Hideto Hidaka MCU Technology Division, Renesas Technology Corporation, 4-1 Mizuhara, Itami, 664-0005, Japan, [email protected] Shoichiro Kawashima Fujitsu Microelectronics Limited, System Micro Division, 1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki, 211-8588, Japan [email protected] Donghyun Kim KAIST Rob A. Rutenbar Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA, [email protected] Amith Singhee IBM, Thomas J. Watson Research Center, Yorktown Heights, NY, USA Naveen Verma Massachusetts Institute of Technology, Cambridge, MA, USA, [email protected] Hiroyuki Yamauchi Fukuoka Institute of Technology, Fukuoka, Japan Hoi Jun Yoo KAIST Kevin Zhang Intel Corporation, Hillsboro, OR, USA vii Chapter 1 Introduction Kevin Zhang Advancement of semiconductor technology has driven the rapid growth of very large scale integrated (VLSI) systems for increasingly broad applications, includ- ing high-end and mobile computing, consumer electronics such as 3D gaming, multi-function or smart phone, and various set-top players and ubiquitous sensor and medical devices. To meet the increasing demand for higher performance and lower power consumption in many different system applications, it is often required to have a large amount of on-die or embedded memory to support the need of data bandwidth in a system. The varieties of embedded memory in a given system have also become increasingly more complex, ranging from static to dynamic and volatile to nonvolatile. Among embedded memories, six-transistor (6T)-based static random access memory (SRAM) continues to play a pivotal role in nearly all VLSI systems due to its superior speed and full compatibility with logic process technology. But as the technology scaling continues, SRAM design is facing severe challenge in maintain- ing sufficient cell stability margin under relentless area scaling. Meanwhile, rapid expansion in mobile application, including new emerging application in sensor and medical devices, requires far more aggressive voltage scaling to meet very strin- gent power constraint. Many innovative circuit topologies and techniques have been extensively explored in recent years to address these challenges. Dynamic random access memory (DRAM) has long been an important semi- conductor memory for its well-balanced performance and density. With increasing demand for on-die dense memory, one-transistor and one-capacitor (1T1C)-based DRAM has found varieties of embedded applications in providing the memory bandwidth for system-on-chip (SOC) applications. With increasing amount of on- die cache memory for high-end computing and graphics application, embedded DRAM (eDRAM) is becoming a viable alternative to SRAM for large on-die memory. To meet product requirements for eDRAM while addressing continuous technology scaling, many new memory circuit design technologies, which are often K. Zhang (B) Intel Corporation, 2501 NE 229th Ave, Hillsboro, OR 97124, USA e-mail: [email protected] K. Zhang (ed.), Embedded Memories for Nano-Scale VLSIs,SeriesonIntegrated 1 Circuits and Systems, DOI 10.1007/978-0-387-88497-4 1, C Springer Science+Business Media, LLC 2009 2 K. Zhang drastically different from commodity DRAM design, have to be developed to sub- stantially improve the eDRAM performance while keeping the overall power con- sumption at minimum. Solid-state nonvolatile memory (NVM) has played an increasingly important role in both computing and consumer electronics. Many new applications in most recent consumer electronics and automobiles have further broadened the embedded appli- cation for NVM. Among various NVM technologies, floating-gate-based NOR flash has been the early technology choice for embedded logic applications. With tech- nology scaling challenges in the floating-gate technologies, including the increasing need for integrating NVM along with more advanced logic transistors, varieties of NVM technologies have been extensively explored, including alternative technol- ogy based on charge-trapping mechanism (Fig. 1.1). More efficient circuit design techniques for embedded flash also have to be explored to achieve optimal product goals. With increasing demand of NVM for further scaling of the semiconductor technology, several emerging memory technologies have drawn increasingly more attention, including magnetic RAM (MRAM), phase-change RAM (PRAM), and ferroelectric RAM (FeRAM). These new technologies not only address some of the fundamental scaling limits in the traditional solid-state memories, but also have brought new electrical characteristics in the nonvolatile memories on top of the random accessing capability. For example, MRAM can offer significant speed improvement over traditional floating-gate memory, which could open up whole new applications. FeRAM can operate at lower voltage and consume ultra low power, which has already made it into “smart-card” marketplace today. These new memory technologies also require a new set of circuit topologies and sensing tech- niques to maximize the technology benefits, in comparison to the traditional NVM design. With rapid downward scaling of the feature size of memory device by tech- nology and drastic upward scaling of number of storage elements per unit area, process-induced variation in memory has become increasingly important for both memory technology and circuit design. Statistical design methodology has now 75 65 NMOS σVTN 55 (one device) 45 Minimum device (mV) T V 35 σ 25 Nominal device 15 Fig. 1.1 Transistor variation trend with technology 5 scaling [1] 130nm 90nm 65nm 45nm 1 Introduction 3 Fig. 1.2 Relative performance among different types of embedded memories become essential in developing reliable memory for high-volume manufacturing. The required statistical