AMD64 Technology AMD64 Architecture Programmer’s Manual Volume 1: Application Programming Publication No. Revision Date 24592 3.09 September 2003 AMD64 Technology 24592—Rev. 3.09—September 2003 © 2002, 2003 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular pur- pose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD arrow logo, and combinations thereof, and 3DNow! are trademarks, and AMD-K6 is a registered trademark of Advanced Micro Devices, Inc. MMX is a trademark and Pentium is a registered trademark of Intel Corporation. Windows NT is a registered trademark of Microsoft Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 24593—Rev. 3.09—September 2003 AMD 64-Bit Technology Contents Figures . .xi Tables . xv Revision History . xvii Preface . .xix About This Book . xix Audience . xix Contact Information. xix Organization . xx Definitions. xx Related Documents . .xxxi 1 Overview of the AMD64 Architecture . 1 1.1 Introduction . 1 New Features . 1 Registers. 3 Instruction Set . 4 Media Instructions . 5 Floating-Point Instructions. 6 1.2 Modes of Operation. 7 Long Mode . 7 64-Bit Mode . 8 Compatibility Mode . 9 Legacy Mode . 9 2 Memory Model . 11 2.1 Memory Organization . 11 Virtual Memory . 11 Segment Registers. 12 Physical Memory . 13 Memory Management . 14 2.2 Memory Addressing . 16 Byte Ordering. 16 64-bit Canonical Addresses . 18 Effective Addresses. 18 Address-Size Prefix . 21 RIP-Relative Addressing. 22 2.3 Pointers . 22 Near and Far Pointers . 23 2.4 Stack Operation. 23 2.5 Instruction Pointer . 24 3 General-Purpose Programming. 27 Contents iii AMD 64-Bit Technology 24593—Rev. 3.09—September 2003 3.1 Registers. 27 Legacy Registers . 28 64-Bit-Mode Registers . 30 Implicit Uses of GPRs . 34 Flags Register . 37 Instruction Pointer Register. 41 3.2 Operands . 41 Data Types . 41 Operand Sizes and Overrides . 44 Operand Addressing . 46 Data Alignment . 47 3.3 Instruction Summary . 48 Syntax . 48 Data Transfer . 49 Data Conversion. 54 Load Segment Registers . 58 Load Effective Address. 58 Arithmetic . 59 Rotate and Shift . 61 Compare and Test . 64 Logical . 67 String . 68 Control Transfer . 69 Flags . 75 Input/Output . 76 Semaphores . 78 Processor Information. 79 Cache and Memory Management . 79 No Operation . 80 System Calls. 80 3.4 General Rules for Instructions in 64-Bit Mode. 81 Address Size. 81 Canonical Address Format . 81 Branch-Displacement Size . 82 Operand Size . 82 High 32 Bits . 83 Invalid and Reassigned Instructions . 83 Instructions with 64-Bit Default Operand Size. 84 3.5 Instruction Prefixes. 85 Legacy Prefixes . 85 REX Prefixes . 89 3.6 Feature Detection . 90 3.7 Control Transfers . 93 Overview. 93 Privilege Levels . 93 Procedure Stack. ..