Sparc Assembly Directives&Branching CS217 Sparc AssemblyReview CCode Assemblycode x=a+5000; seta,%i1 ld[%i1],%g1 set5000,%g2 ? add%g1,%g2,%g1 setx,%i1 st %g1,[%i1] 1 StilltoLearn • Howdo“definevariables” • Howtoimplementcontrolstructures • Howtodefineandcallfunctions • Otherdetails AAsssseemmbblleerrDDiirreeccttiivveess AssemblerDirectives • Identifysections • Allocate/initializememory • Makesymbolsexternallyvisible 2 IdentifyingSections • Text(.section“.text”) 0 Containscode(instructions) OS Defaultsection 0x2000 Text • Read-OnlyData(.section“.rodata”) Data Containsconstants BSS • Read-WriteData(.section“.data”) Heap Containsuser-initializedglobalvariables • BSS(.section“.bss”) Blockstartingsymbol Containszero-initializedglobalvariables Stack 0xffffffff Sections(cont) • Eachsectionhasownlocationcounter Locationcounterisupdatedwhenassembler processesdirectiveorinstruction add and sethi T or e x text_lc ld t 0 1 D data_lc a t a 3 Allocatingmemory • Incrementlocationcounterbynbytes .skip nbytes .section“.bss” var1:.skip16 .section“.data” var2:.skip4 Initializingmemory • Incrementlocationcounterandinitializedata .bytebyteval1[,byteval2...] .halfhalfval1[,halfval2...] .wordwordval1[,wordval2...] .section“.data” sethi T sum:.word0 or e x ld t .section“.text” setsum,%o0 D ld[%o0],%i1 a sum: 0 t a 4 InitializingASCIIData • Specialdirectivesforasciidata .byte150,145,154,154,157,0 .ascii“hello” .byte0 .asciz “hello” MakingSymbolsExternallyVisible • Markvariablesasglobal .global .section“.data” .align4 .globalmonth month:.word jan, feb,mar, apr,may, jun .word jul, aug,sep, oct, nov, dec jan:.asciz “January” feb:.asciz “February” mar:.asciz “March” apr:.asciz “April” may:.asciz “May” jun:.asciz “June” jul:.asciz “July” ... 5 MakingSymbolsExternallyVisible • Markfunctionsasglobal .global .section“.rodata” fmt:.asciz “Hello,world\n” .section“.text” .align4 .globalmain main:save%sp,-96,%sp set fmt,%o0 call printf nop mov 1,%g1 ta 0 ret restore .section“.data” Example1 a:.word1,2 .byte`C’ .align2 structexample{ .half3,4 inta,b; .align4 chard; .word6,7 shortx,y; intu,v; .section“.text” }; .align4 .globalmain structexamplea= main:save%sp,-96,%sp { 1,2, seta,%l0 ‘C’, ld[%l0+0],%l1 4,5, ld[%l0+4],%l2 6,7 ldub [%l0+8],%l3 }; ldsh [%l0+10],%l4 mov 1,%g1 main() ta 0 { ret … restore } 6 .section“.bss” Example2 a:.skip4*100 .section“.text” inta[100]; .align4 .globalmain main() main:save%sp,-96,%sp { … clr %l0 L1: cmp %l0,%l1 } bge L2;nop ... sll%l0,2,%l2 ld[a+%l2],%l3 ? ... inc%l0 ba L1; nop L2: mov 1,%g1 ta 0 ret restore Branches • Instructionsnormallyfetchedandexecuted fromsequentialmemorylocations PC istheaddressofthecurrentinstruction nPC istheaddressofthenextinstruction nPC =PC+4 • Branchesandcontroltransferinstructions changenPC tosomethingelse ba labelnPC=label bge label if(lastcomparewas“greaterorequal”) nPC=label else nPC=PC+4 7 BranchInstructions • Setprogramcounter(PC)conditionally a n b{,a}label .. z 00 a cond 010 disp22 31 29 28 24 21 • Ifbranchistaken… nPC =PC+4* signextend(disp22) targetisaPC-relativeaddress where PCistheaddressofthebranchinstruction • Decisiontobranchisbasedonintegerconditioncodes IntegerConditionCodes • ProcessorStateRegister(PSR) ... icc ... 31 23 20 • Integerconditioncodes(icc) N setifthelastALUresultwasnegative Z setifthelastALUresultwaszero V setifthelastALUresultwasoverflowed C setifthelastALUinstructionthatmodifiedthe icc causedacarryoutof,oraborrowinto,bit31 8 CarryandOverflowConditionCodes • Ifthecarrybitisset thelastadditionresultedinacarry,or thelastsubtractionresultedinaborrow Usedformulti-wordaddition addcc%g3,%g5,%g7 themostsignificantword addxcc%g2,%g4,%g6 isintheevenregister (%g6,%g7)=(%g2,%g3)+(%g4,%g5) • Iftheoverflowbitisset resultofsubtraction(orsigned-addition)doesn’tfit CCInstructions • Arithmeticoperations addcc src1,src2,dst dst =src1+src2 subcc src1,src2,dst dst =src1- src2 • Logicaloperations andccsrc1,src2,dst dst = src1& src2 orccsrc1,src2, dst dst = src1| src2 xorccsrc1,src2, dst dst = src1^ src2 • Syntheticinstructions tstreg orccreg,%g0,%g0 btstbits,reg andccreg,bits,%g0 cmpsrc1,src2 subcc src1,src2,%g0 cmpsrc,value subccsrc,value,%g0 9 BranchInstructions • Unconditionalbranches(andsynonyms) bajmpbranchalways bnnopbranchnever • Rawcondition-codebranches bnz !Z bz Z bpos !N bneg N bcc !C bcs C bvc !V bvs V BranchingInstructions(cont) • Comparisonbranches instruction signed unsigned be Z Z bne !Z !Z bgbgu !(Z|(N^V)) !(C|Z)) blebleu Z|(N^V) C|Z bgebgeu !(N^V) !C blblu N^V C 10 BranchingExamples • if-then-else if(a>b) #definea%l0 c=a; #defineb%l1 else #definec%l2 c=b; cmp a,b ble L1;nop mov a,c ba L2;nop L1:movb,c L2:... BranchingExamples(cont) • Loops for(i=0;i<n;i++) #definei%l0 ... #definen%l1 clr i L1:cmpi,n bge L2;nop ... inci ba L1;nop L2: 11 BranchingExamples(cont) • Loops(alternativeimplementation) for(i=0;i<n;i++) #definei%l0 ... #definen%l1 clr i ba L2;nop L1:... inci L2:cmpi,n bl L1;nop .section“.bss” Example2(again) a:.skip4*100 .section“.text” inta[100]; .align4 .globalmain main() main:save%sp,-96,%sp { … clr %l0 L1: cmp %l0,%l1 } bge L2;nop ... sll%l0,2,%l2 ld[a+%l2],%l3 ... inc%l0 ba L1; nop L2: mov 1,%g1 ta 0 ret restore 12 MoreControlTransferInstructions • Controltransferinstructions instruction type addressingmode biccconditionalbranch PC-relative jmpl jumpandlink registerindirect rett returnfromtrap registerindirect call procedurecall PC-relative ticctraps registerindirect (vectored) PC-relativeaddressingislikeregister displacementaddressingthatusesthePC asthebaseregister MoreControlTransferInstructions • Branchinstructions op a cond op2 disp22 nPC=PC+signextend(disp22)<<2 • Calls op disp30 nPC=PC+signextend(disp30)<<2 position-independent codedoesnotdependonwhere it’sloaded;usesPC-relativeaddressing 13 Summary • Assemblylanguagedirectives Definesections Allocatememory Providelabelsforvariables,branches,etc. Controlwhetherlabelsareexternallyvisible • Branchinstructions SetnPCconditionallybasedonintegerconditioncodes ICCs setbyarithmeticandlogicalinstructions Branchaddressesarerelative(atmost22bitsaway) • Othercontroltransferinstructions Describedinnextfewlectures 14.