CALIFORNIA STATE UNIVERSITY, NORTHRIDGE A TOMASULO BASED MIPS SIMULATOR A graduate project submitted in partial fulfillment of the requirement For the degree of Master of Science In Electrical Engineering By Reza Azimi May 2013 Signature Page The graduate project of Reza Azimi is approved: ____________________________________ _____________ Ali Amini, Ph.D. Date ____________________________________ _____________ Shahnam Mirzaei, Ph.D. Date ____________________________________ _____________ Ramin Roosta, Ph.D., Chair Date California State University, Northridge ii Acknowledgement I would like to thank Dr. Shahnam Mirzaei for providing nice ideas to work upon and Dr. Ramin Roosta for his guidance. I sincerely want to thank my other committee member Dr. Ali Amini for his support as a member of project committee. I would like to show gratitude to all of my project committee members for being great mentors and their continuous guidance. Most importantly, I like to thank my family for their endless support, unconditional love and great care throughout my life. iii Table of Contents Signature Page .................................................................................................................... ii Acknowledgement ............................................................................................................. iii List of Figures ..................................................................................................................... v List of Tables ..................................................................................................................... vi ABSTRACT ...................................................................................................................... vii Chapter 1 : Introduction ...................................................................................................... 1 1.1 RISC Versus CISC: .............................................................................................. 1 1.2 MIPS: ........................................................................................................................ 3 1.3Design Environment: ................................................................................................. 4 Chapter 2 : Pipelining ......................................................................................................... 6 2.1 A Simple Implementation of RISC: .......................................................................... 7 2.2 The Classic Five Stage Pipeline:............................................................................... 8 2.3 Pipeline Hazards: .................................................................................................... 10 2.4 Assume Branch Not Taken: .................................................................................... 12 2.5 Data Forwarding: .................................................................................................... 12 2.6 MIPS Implementation: ............................................................................................ 14 Chapter 3 : Dynamic Scheduling ...................................................................................... 18 3.1 Tomasulo’s Algorithm ............................................................................................ 20 3.2 Applications ............................................................................................................ 26 Chapter 4 : Design Implementation .................................................................................. 27 4.1 Pipelined MIPS: ...................................................................................................... 27 4.2 Tomasulo: ............................................................................................................... 35 Chapter 5 : Analysis and Conclusion ................................................................................ 38 5.1 Pipelined MIPS Simulation Example: .................................................................... 38 5.2 Tomasuolo’s Algorithm Simulation Example: ....................................................... 51 5.3 Conclusion: ............................................................................................................. 60 5.4 Future Enhancement: .............................................................................................. 60 References ..................................................................................................................... 61 Appendix: Source Codes............................................................................................... 62 iv List of Figures Figure 2-1 RISC Data Path ................................................................................................. 9 Figure 2-2 Forwarding Paths for the Given Example ....................................................... 13 Figure 2-3 The Implemented Pipelined MIPS Architecture ............................................. 17 Figure 3-1 Tomasulo Based Processor Structure .............................................................. 23 Figure 4-1 Designed User Interface for Pipelined MIPS .................................................. 27 Figure 4-2 Pipelined MIPS Simulator Flow Chart ........................................................... 34 Figure 4-3 Designed User Interface for Tomasulo’s Algorithm Implementation ............ 35 Figure 4-4 Tomasulo’s Algorithm Simulator Flow Chart ................................................ 37 Figure 5-1 Pipelined MIPS Simulation in the First Clock Cycle...................................... 41 Figure 5-2 Pipelined MIPS Simulation in the Fifth Clock Cycle ..................................... 42 Figure 5-3 Pipelined MIPS Simulation in the Ninth and Tenth Clock Cycle ................... 43 Figure 5-4 Pipelined MIPS Simulation in the Eleventh Clock Cycle ............................... 44 Figure 5-5 Pipelined MIPS Simulation in the Fifteenth and Sixteenth Clock Cycle........ 45 Figure 5-6 Pipelined MIPS Simulation in the Nineteenth Clock Cycle ........................... 46 Figure 5-7 Tomasulo’s Algorithm Simulation in the First Clock Cycle .......................... 52 Figure 5-8 Tomasulo’s Algorithm Simulation in the Second and Third Clock Cycle ..... 53 Figure 5-9 Tomasulo’s Algorithm Simulation in the Forth Clock Cycle ......................... 54 Figure 5-10 Tomasulo’s Algorithm Simulation in the Fifth and Sixth Clock Cycle ........ 55 Figure 5-11 Tomasulo’s Algorithm Simulation in the Seventh and Eighth Clock Cycle 56 Figure 5-12 Tomasulo’s Algorithm Simulation in the tenth Clock Cycle ........................ 57 Figure 5-13 Tomasulo’s Algorithm Simulation in the Sixteenth Clock Cycle ................. 58 Figure 5-14 Tomasulo’s Algorithm Simulation in the 56th and 57th Clock Cycle ............ 59 v List of Tables Table 1-1 Format I Instruction Fields ................................................................................. 4 Table 1-2 Format R Instruction Fields ................................................................................ 4 Table 4-1 Supported Instructions Information .................................................................. 32 Table 5-1 Pipelined MIPS Simulation Example ............................................................... 38 Table 5-2 Expected Result from the Given Example to the Pipelined MIPS Simulator .. 39 vi ABSTRACT A Tomasulo Based MIPS Simulator By Reza Azimi Master of Science in Electrical Engineering From 1985 processor designers are using pipeline to cover the instructions execution on each other and increase their design speed. They call this overlap between instructions, “instruction level parallelism” because instructions are calculated in parallel. For developing ILP, there are two main separate methods: First method use hardware to detects and takes advantage dynamically the parallelism and the second method uses software to statically find parallelism at compile time. The processors which used the dynamic hardware based method like the Intel Pentium family are more successful in the market. Robert Tomasulo developed the Tomasulo algorithm for IBM 360/91 floating point. It is a hardware based algorithm which handles out of order execution problems. This project describes the design and implementation of a simulator for a Tomasulo based MIPS architecture processor and its fundamental ideology and needed techniques. The principles of dynamic scheduling and Tomasulo’s algorithm are explained. The main features of the simulator are defined and important hazards, which we have to deal with them along with the implementation, and their solutions are mentioned. The implemented simulator is described with its core components and most important functions. The simulator developed using C++ and on a Qt framework. vii Chapter 1 : Introduction 1.1 RISC Versus CISC: Reduced Instruction Set Computer (RISC) architecture’s goal is to reduce the number and complexity of instruction in the processors. RISC developers use many techniques to exploit caching, superscalarity, pipelining and etc. in their processor architecture. These techniques are described in the following paragraphs. One instruction per cycle: The main idea and concept of RISC is only having one instruction per each clock cycle. This is the most important feature of early RISC designs that every instruction complete in a single clock cycle. Fixed instruction Length: Since one instruction has to issue per each clock