Full-service, independent repair center -~ ARTISAN® with experienced engineers and technicians on staff. TECHNOLOGY GROUP ~I We buy your excess, underutilized, and idle equipment along with credit for buybacks and trade-ins. Custom engineering Your definitive source so your equipment works exactly as you specify. for quality pre-owned • Critical and expedited services • Leasing / Rentals/ Demos equipment. • In stock/ Ready-to-ship • !TAR-certified secure asset solutions Expert team I Trust guarantee I 100% satisfaction Artisan Technology Group (217) 352-9330 | [email protected] | artisantg.com All trademarks, brand names, and brands appearing herein are the property o f their respective owners. Find the Oracle / Sun Microsystems UltraSPARC-II at our website: Click HERE UltraSPARC User’s Manual UltraSPARC-I UltraSPARC-II July 1997 Sun Microelectronics 901 San Antonio Road Palo Alto, CA 94303 Part No: 802-7220-02 This July 1997 -02 Revision is only available on- line. The only changes made were to support hypertext links in the pdf file. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com Copyright © 1997 Sun Microsystems, Inc. All Rights Reserved. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED “AS IS” WITHOUT ANY EXPRESS REPRESENTATIONS OR WARRANTIES. IN ADDITION, SUN MICROSYSTEMS, INC. DISCLAIMS ALL IMPLIED REPRESENTATIONS AND WARRANTIES, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON- INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. This document contains proprietary information of Sun Microsystems, Inc. or under license from third parties. No part of this document may be reproduced in any form or by any means or transferred to any third party without the prior written consent of Sun Microsystems, Inc. Sun, Sun Microsystems, and the Sun logo are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. The information contained in this document is not designed or intended for use in on-line control of aircraft, air traffic, aircraft navigation or aircraft communications; or in the design, construction, operation or maintenance of any nuclear facility. Sun disclaims any express or implied warranty of fitness for such uses. Printed in the United States of America. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com Contents Preface ..................................................................................................................................... 9 Overview ...................................................................................................................... 9 A Brief History of SPARC .......................................................................................... 9 How to Use This Book ................................................................................................ 10 Section I — Introducing UltraSPARC 1. UltraSPARC Basics................................................................................................................ 3 1.1 Overview ...................................................................................................................... 3 1.2 Design Philosophy ...................................................................................................... 3 1.3 Component Overview ................................................................................................ 5 1.4 UltraSPARC Subsystem.............................................................................................. 10 2. Processor Pipeline ................................................................................................................. 11 2.1 Introductions................................................................................................................11 2.2 Pipeline Stages ............................................................................................................. 12 3. Cache Organization .............................................................................................................. 17 3.1 Introduction.................................................................................................................. 17 4. Overview of the MMU ......................................................................................................... 21 4.1 Introduction.................................................................................................................. 21 4.2 Virtual Address Translation ...................................................................................... 21 Section II — Going Deeper 5.Artisan Cache Technology and Memory Group -Interactions Quality Instrumentation........................................................................................ ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 27 5.1 Introduction.................................................................................................................. 27 Sun Microelectronics iii UltraSPARC User’s Manual 5.2 Cache Flushing............................................................................................................. 27 5.3 Memory Accesses and Cacheability ......................................................................... 29 5.4 Load Buffer................................................................................................................... 39 5.5 Store Buffer................................................................................................................... 40 6. MMU Internal Architecture ................................................................................................ 41 6.1 Introduction.................................................................................................................. 41 6.2 Translation Table Entry (TTE) ................................................................................... 41 6.3 Translation Storage Buffer (TSB)............................................................................... 44 6.4 MMU-Related Faults and Traps................................................................................ 47 6.5 MMU Operation Summary........................................................................................ 50 6.6 ASI Value, Context, and Endianness Selection for Translation............................ 52 6.7 MMU Behavior During Reset, MMU Disable, and RED_state ............................. 54 6.8 Compliance with the SPARC-V9 Annex F............................................................... 55 6.9 MMU Internal Registers and ASI Operations ......................................................... 55 6.10 MMU Bypass Mode..................................................................................................... 68 6.11 TLB Hardware.............................................................................................................. 69 7. UltraSPARC External Interfaces......................................................................................... 73 7.1 Introduction.................................................................................................................. 73 7.2 Overview of UltraSPARC External Interfaces......................................................... 73 7.3 Interaction Between E-Cache and UDB.................................................................... 76 7.4 SYSADDR Bus Arbitration Protocol......................................................................... 84 7.5 UltraSPARC Interconnect Transaction Overview .................................................. 92 7.6 Cache Coherence Protocol.......................................................................................... 94 7.7 Cache Coherent Transactions .................................................................................... 102 7.8 Non-Cached Data Transactions................................................................................. 109 7.9 S_RTO/S_ERR ............................................................................................................. 111 7.10 S_REQ............................................................................................................................ 111 7.11 Writeback Issues .......................................................................................................... 112 7.12 Interrupts (P_INT_REQ)............................................................................................. 116 7.13 P_REPLY and S_REPLY.............................................................................................. 117 7.14 Multiple Outstanding Transactions.......................................................................... 126 7.15 Transaction Set Summary........................................................................................... 129 7.16 Transaction Sequences................................................................................................ 131 7.17 Interconnect Packet Formats...................................................................................... 138 7.18 WriteInvalidate ...........................................................................................................