COMSAT Technical Review Volume 17 Number 1, Spring 1987 Advisory Board Joseph V. Charyk COMSAT TECHNICAL REVIEW John V. Evans Spring 1987 Editorial Board Geoffrey Hyde, Chairman Volume 17 Number 1 , Richard A. Arndt Ali E. Atia S. Joseph Campanella I DESIGN AND MODELING OF A GaAs MONOI.I'THIC 2- TO 6-GHz Dattakumar M. Chitre R. K. Gupta , .1. H. Reynolds, Russell J. Fang FEEDBACK AMPLIFIER Howard W. Flieger M. C. Fu , AND T. Heikkila Melvyn Grossman 23 A 120-Mbit/s TDMA QPSK MODEM FOR ON-BOARD APPLICATIONS Ivor N. Knight , AND F. T. Assal Larry C. Palmer R. G. Egri , K. Karimullab Edward E. Reinhart 55 AN ADAPTIVE EQUALIZER FOR 120-Mblt/s QPSK TRANSMISSION David V. Rogers Hans J. Weiss J. M. Kappes Albert E. Williams 87 MODULATION SELECTION FOR ILL MOBILE SATELI,FI'F EXPERIMENT Pier L. Bargellini, Editor Emeritus (MSAT-X) K. M. Mackenthun Editorial Staff MANAGING EDITOR Margaret B. Jacocks 105 HURWrrZ STABII .II'Y ANALYSIS OF AN ADPCM SYSTEM TECHNICAL EDITORS S. Dimolitsas AND U. Bhaskar Barbara J. Wassell Diane Haugen APPROXIMATIONS FOR THE RAISED COSINE FILTER PRODUCTION 127 POLE-ZERO J. J. Poklemba Barbara J. Wassell FAMILY Louis P. Stephens, Jr. 159 A SIMULATION STUDY OF RAIN ATTENUATION AND DIVERSITY EFFECTS CIRCULATION LINKS J. Mass Shirley H. Taylor ON SATELLITE COMSAT TECHNICAL REVIEW is published twice a year by 189 PROGRAMMABL E CONVOLUTIONAL ENCODER AND THRESHOLD Communications Satellite Corporation (COMSAT). Subscriptions, DECODER J. S. Snyder which include the two issues published within a calendar year, are: one year, $15 U.S.; two years, $25; three years, $35; 201 CTR NOTE : GEOSTATIONARY SATELLITE LOG FOR YEAR END 1986 single copies, $10; article reprints, $2.50. Overseas air mail C. H. Schmitt delivery is available at an additional cost of $18 per year. Make checks payable to COMSAT and address to Records Department, 267 TRANSLATIONS OF ABSTRACTS Communications Satellite Corporation, 22300 Comsat Drive, FRENCH 267 SPANISH 272 Clarksburg, MD 20871-9475, U.S.A. ISSN 0095-9669 277 AUTHOR INDEX, CTR 1986 COMMUNICATIONS SATELLITE CORPORATION 1987 COMSAT IS AIRADE MARK AND SERVICE MARK 279 LNDEX OF 1986 PUBLICATIONS BY COMSAT AUTHORS 01 HIE COMMUNICATIONS SATELLITE CORPORATION 111 Index: amplifiers, integrated circuits, ion implantation, MMICs, models, transistors Design and modeling of a GaAs monolithic 2- to 6-GHz feedback amplifier R. K. GUPTA, J. H. REYNOLDS, M. C. Fu, AND T. HtiKKILA (Manuscript receives December 3, 1986) Abstract The design, fabrication, and performance of a monolithic 2- to 6-GHz feedback amplifier module are described, with particular emphasis on the modeling approaches used during the design and fabrication phases. The amplifier design is based on GaAs field-effect transistor (rET) equivalent circuit parameters derived from known ion implantation profile, peak doping density, and device geometries. Measured parametric data obtained from test patterns arc used to monitor and control the fabrication process. Both measured and modeled DC and Rr parameters of the FEi, as well as amplifier performance results, are presented for two process wafers. Agreement between the measured and modeled gain of the feedback amplifier was within I dB over a broad I- to I1-GHz frequency band. Introduction The use of GaAs monolithic microwave integrated circuits (MMles) in communications systems holds great promise for enhancing system reliability while reducing mass, volume, and cost [11,[2]. However, the design and fabrication cycle for MM1c modules is relatively long and expensive compared to that of conventional hybrid circuits. In order to reduce development costs and enhance the probability of success in a single fabrication itineration, a thorough understanding of field-effect transistor (FET) models, from basic 1 GaAs MONOLITIBC 2- TO 6-GRZ FEEDBACK AMPLIFIER 3 2 COMSAT TECHNICAL REVIEW VOLUME 17 NUMBER 1, SPRING 1987 device physics through the fabrication process, design methods, and circuit CIRCUIT PERFORMANCE modeling, is required. REQUIREMENTS This paper presents the design, fabrication, and performance of an MMIC 2- to 6-GHz feedback amplifier module developed at COMSAT Laboratories. IMPLANT PROFILE / DEVICE SELECTION The design strategies and modeling approaches used during various MMIC MATERIAL DATA (CHANNEL GEOMETRIES) development phases are discussed. A PET equivalent circuit was first derived for a known ion implant profile, peak doping density, gate recess depth, and DEVICE RF EQUIVALENT DC CHARACTERISTICS CIRCUIT other fabrication parameters. The amplifier was then designed with maximum tolerance to process variations and with simple on-chip tuning to adjust for SELECTION OF the most sensitive parameters. The modeling process described here is useful MATCHING NETWORKS for selecting optimum FET geometries, designing the circuit for desired performance, and defining target values for critical process parameters and CAD DESIGN / MODELING adjusting these values during fabrication. In addition, accurate modeling of device Dc current and transfer characteristics allows a priori selection of device operating conditions for self-bias operation. SENSITIVITY ANALYSIS General design considerations The design of broadband feedback amplifiers requires LET devices with SATISFIES large transconductance [3]-[6]. This can be achieved by increasing the device FABRICATION TOLERANCES width and carrier concentration and decreasing the gate length. Larger device width also results in larger Dc power dissipation and larger gate-to-source capacitance, Cgf, which tend to degrade the open-loop gain at higher frequencies. Therefore, FETs with smaller gate lengths and a higher trans- CIRCUIT LAYOUT AND MASK MAKING conductance (gm)-to-Cgs ratio are desirable. Based on these considerations, a FET with a nominal gate length of 0.5 (or 0.6) µm and width of 300 [um was selected for this design. This FET geometry was consistent with other WAFER PROCESSING circuits on the same mask set, which included a low-noise amplifier ]7], a dual-gate FET switch with a level translator, and an amplifier with passive IN-LINE PARAMETRIC TESTS FET switching at its input and output. PROCESS To increase the yield, the MMIC design must be tolerant to fabrication ADJUSTMENTS parameter variations associated with process uncertainties. Therefore, a major COMPLETION OF FRONT-SIDE PROCESSING portion of the design effort involved developing accurate models for the active devices and the matching components, and establishing their sensitivity WAFER-LEVEL PROBING, to process variations. Figure 1 is a flow-chart of a typical MMIC design cycle. THINNING, DICING The design begins with device selection for desired electrical performance, and includes device modeling, design of matching networks, sensitivity analysis for acceptable performance, circuit layout, and mask-making. Circuit fabrication consists of processing the various mask layers, in-line parametric testing, fabrication adjustments, DC probing, thinning, and dicing. Because of the time consumed by each mask fabrication and processing cycle, it is Figure 1. Flowchart of the MMIC Design, Modeling, and Fabrication essential that a design be relatively insensitive to fabrication tolerances. Cycle 4 COMSAT TECHNICAL REVIEW VOLUME 17 NUMBER 1, SPRING 1987 GaAs MONOLITHIC 2- TO 6-GHZ FEEDBACK AMPLIFIER 5 FET modeling A number of models have been used at COMSAT Laboratories for the dP design of FETs and circuits [8],[9]. The FET model described here is based on device physics , with many refinements derived from measurements of a prototype device. For this design , the target Gaussian profile shown in Figure 2a was used with the following profile parameters: • Peak carrier density, He 2.7 x 1017 cm3 • Peak location , d„ 0.11 µm • Standard deviation , BE 0.065 p.m A recess depth up to the peak of the profile (0.11 µm), as shown in Figure 2b, results in a pinchoff voltage of approximately - 1.5 V and makes the De and RE device characteristics relatively insensitive to profile parameters. This profile information and measurements on the prototype device were as IJ do used to obtain the device equivalent circuit shown in Figure 3. Most of the 0 01 0.2 0.3 04 0.5 intrinsic FET elements, including junction capacitance, input resistance, and DISTANCE FROM ORIGINAL SURFACE (pm) device transconductance, were computed from the basic device physics. (a) Original Profile Output resistance, parasitic capacitances, and resistances were obtained from device geometries and measurements. 1018 I I I Junction capacitance, C, is modeled as the capacitance of the velocity- n„ ,P saturated region under the gate. Geometric inter-electrode capacitance caused by electrostatic coupling between the gate, source, and drain electrodes was computed as described by Pucel et al. [10]. Gate-to-N' and N'-to-N' (rather than gate-to-ohmic and ohmic-to-ohmic) gap dimensions were used. The N- 1017 material is sufficiently conductive to maintain an equi-potential surface over the short distances involved. A sidewall capacitance, which accounts for the extension of the depletion region toward the source, must be added to the gate-to-source fringing capacitance. The junction sidewall capacitance com- puted by the model is 0.04 pF and is included in the Cg of the device 1016 equivalent circuit. Input resistance, R;., represents a charging resistance corresponding to the gate-to-source capacitance. It is usually derived from an electron transit time, T, using resistance-capacitance (RC) time-constant relation as I do 1015 '{ I 0 0.1 0.2 0.3 0.4 R;,, = TICg, (I ) DISTANCE FROM ETCHED SURFACE (pm) The transit time is defined by (b) Profile After Recess Etch Figure 2. Gaussian ]on Implantation Profiles for the MMIC T=L,IV,. Feedback Amplifier GaAs MONOLITHIC 2- To 6-GHL FEEDBACK AMPLIFIER 7 6 COMSAT TECHNICAL REVIEW VOLUME 17 NUMBER 1, SPRING 1987 where V is the saturated velocity and L, is an empirically determined transit length. In the model, 16 = 1.2 X 107 cm/s and L, = 0.7 µm (geometric 0 gate length) were used. Transconductance, g,, is computed from basic device physics and is dependent on carrier profile, saturation velocity, and gate width.