UDC 621.3.049.771.14.001.63 Verification Methodology for a Complex System-on-a-Chip VAkihiro Higashi VKazuhide Tamaki VTakayuki Sasaki (Manuscript received December 1, 1999) Semiconductor technology has progressed to the point where it is now possible to implement system-level functions on a single LSI chip. However, traditional LSI verifi- cation becomes less and less powerful as the scale and complexity increase. In fact, more than half of the time required to develop a System-on-a-Chip (SOC) is used for function verification. A new verification methodology for SOCs should therefore be established. We developed a system-level simulation technology to verify the specification and architecture of an SOC and a logic emulation technology to verify the logic function of an entire SOC. By combining these technologies, we established a powerful verifica- tion methodology for an SOC. We applied the verification methodology to develop a high-definition MPEG2 decoder LSI for a digital TV broadcasting system. The LSI was successfully developed on schedule and worked in the first silicon implementation completely according to the specifications. 1. Introduction because of this difficulty. In the era of the System-on-a-Chip (SOC), we We therefore examined the bugs that occur are now able to integrate the functions needed for during LSI development and identified the follow- consumer products such as digital home electron- ing causes: ic appliances and advanced mobile devices on a • Specification problems (insufficient definition, single LSI chip. An SOC LSI includes complex lack of necessary conditions, and misunder- functions with millions of logic gates. However, it standings between people) is difficult to verify an SOC effectively using the • Implementation problems (insuficient perfor- traditional LSI verification methodology. mance, improper block partitioning, block One of the most common applications of SOCs interface mismatching, and excessive power is in a video decoder system. It took almost two consumption) years to develop a Moving Picture Experts • Verification problems (slow software simu- Group Phase 2 (MPEG2) decoder LSI. The main lation and problems with the hardware- time-consuming tasks were the logic design/veri- software interface and system function veri- fication (eight months) and several revisions (10 fication) months). In fact, it took a software logic simula- A new design methodology by which an SOC tor 10 hours to simulate a single video frame. can be efficiently designed and verified should be Since a video stream contains 30 frames per sec- established to overcome these problems. The de- ond, it is difficult to develop a fully debugged video sign methodology for an LSI shifted from the processing LSI using traditional LSI design/veri- transistor level in the 1970s to the gate level in fication. The LSI was revised several times the 1980s. Then, in the 1990s, it shifted to the 24 FUJITSU Sci. Tech. J.,36,1,pp.24-30(June 2000) A. Higashi et al.: Verification Methodology for a Complex System-on-a-Chip Register-Transfer Level (RTL), where logic circuits Design Verification Algorithm are described using a Hardware Description System model (3 s/frame) System- Language (HDL). HW/SW partitioning level Specifi- Architecture Architecture simulation We have now established a new design meth- cations model (5 m/frame) odology for SOCs. At the beginning of SOC design, C RTL (Comparison) we introduce a system-level simulation technique. RT level RTL model Hardware ( ) Logic synthesis 10 h/frame emulation A system-level simulation is performed using Gate-level (Simulation time behavioral models written in C/C++ and is very for MPEG2 decoder) fast because the behavioral models are highly abstracted to model entire system functions. The Figure 1 SOC design flow. system-level simulation provides us with a pow- erful methodology to verify the specifications of a system and to check the architecture to realize a an SOC are complex, there is a big gap between System-on-a-Chip. the system-level design and the logic design. Log- We also introduce a hardware emulation sys- ical errors in an RTL can be verified by a logic tem to verify RTL designs. Because a hardware simulator, but specification errors that occur at emulator is 1000 to 10 000 times faster than a system design are fatal. software simulator, we can simulate a frame of a Figure 1 shows our design flow for an SOC. video stream in only one minute using an emula- First, the designer defines the specifications of an tor, whereas it would take 10 hours using a SOC according to the industrial standards, re- software simulator. quired performance, and permissible costs. However, one of the drawbacks of using an Usually, this is a paper plan. We develop the al- emulation system is that it is hard to debug the gorithm models for an SOC in C/C++ and verify circuit being emulated. That is, it is difficult to the specifications and estimate the performance locate bugs in a circuit by checking the outputs of with system-level simulation. Many test scenari- emulation results. To overcome this difficulty, we os are examined at high-speed by the system-level use the results of the system-level simulation men- simulation. tioned above. Generally, an LSI is designed Then, the architecture of the SOC is studied block-by-block. Therefore, if we compare the re- so that the specifications can be satisfied. The sults of the system-level simulation with those of tradeoffs between the hardware processing and the emulation block-by-block, we can easily locate the software implementation for the SOC are also bugs. considered in the architecture design. System-level simulation for specification and The architecture is studied using system- architecture checking, hardware emulation for level simulation again. This time, however, the RTL design verification, and a combination of blocks of the SOC are modeled in cycle-accurate these two for a debugging environment provides models. The cycle-accurate models include cycle- us with a powerful design/verification methodol- accurate timing and the exact data exchange ogy for developing an SOC. This paper describes among blocks. The simulation results are also the system-level simulation technology and the used for reference when the RTL is being verified. emulation technology we used to develop an SOC In the RTL design, the logic functions of the for a digital TV broadcasting system. blocks are described in an RTL language and verified by RTL simulation. Then, they are inte- 2. SOC design methodology grated into a logic circuit for the SOC and Since the specifications and architectures of simulated to verify the interfaces between blocks. FUJITSU Sci. Tech. J.,36, 1,(June 2000) 25 A. Higashi et al.: Verification Methodology for a Complex System-on-a-Chip LSI specifications: broadcasting system and the specifications of the – HDTV (MP@HL) MPEG2 decoder. The system-level simulation – Multi-decode function (4 × SDTV) models the entire system at a high abstraction – Seamless decode & display level and verifies the system performance at high – Noise protection speed.2) We developed models for the specification Broadcasting Broadcasting stage and architecture design stage of the LSI’s station satellite DTV receiver development. We also verified the specifications and estimated the performance by system-level Decoder LSI simulation. (Noise) 3.1.1 Specification simulation Figure 2 We developed the specification models of the BS digital broadcasting system. MPEG2 decoder LSI and the BS digital broadcast- ing system at the algorithm level in C language. It takes a huge amount of time, however, to The algorithm models for the MPEG2 decoder in- simulate an entire SOC using a software simula- cluded a Transport Stream Decoder, MPEG2 tor. We therefore simulate the entire circuit using (Main-Profile at High Level) Video Decoder, a hardware emulation system which runs 1000 and Display. We checked the models by testing times faster than a software simulator. However, about 60 kinds of video streams. it is not so easy to debug a circuit on an emula- Algorithm models of the BS digital broadcast- tion system. We therefore compare the results of ing system were also developed to conform to emulation with the results of the system-level sim- the BS digital broadcasting specifications recom- ulation block-by-block, which makes it easy to mended by the Association of Radio Industries locate errors in a circuit. Business (ARIB). These specifications are trans- Our design/verification methodology for an mission specifications, for example, for program SOC consists, therefore, of a system-level simula- data multiplexing, Reed-Solomon encoding, inter- tion for the specification and architecture check, leaving, Trellis Coded 8 Phase Shift Keying RTL verification using a hardware emulator, and (TC8PSK), Quaternary PSK (QPSK), and Binary a comparison of the two sets of results. PSK (BPSK), for a broadcasting station and for receivers on the ground.3) 3. SOC verification of digital TV decoder LSI Figure 3 shows the block diagram of the BS BS digital broadcasting will start this year digital broadcasting system that was used for the (2000) in Japan to provide high-definition TV specification simulation. The specification simu- broadcasting. BS digital broadcasting will be pro- lation enables us to simulate many complicated vided to each home through the BS-4 broadcasting combinations of broadcasting standards and re- satellite. The video signals will be compressed ac- ception conditions (e.g., rain and lightning). cording to the MPEG2 standard format, digitally 3.1.2 Architecture simulation modulated, and then transmitted. We applied our Next, we developed detailed models at the design methodology to develop a high-definition behavioral level to verify the SOC’s architecture, MPEG2 decoder LSI for the BS digital broadcast- for example, its memory controls and scheduling. ing receiver.1) There are several important requirements when developing models for system-level simulation: 3.1 System-level simulation technology mixed-level models must be suitable for mixed- Figure 2 shows an outline of the BS digital level simulation, the block interface must be 26 FUJITSU Sci.