Custom & Multichip Packaging Contract Manufacturing Micross’ contract assembly offers design and engineering support, BOM procurement, and a wide selection of package, substrate and interposer materials. Micross provides comprehensive semiconductor packaging services for multiple electronic components, including digital, mixed signal, analog, multi-chip and System-in-Package (SiP). We design, build and test hermetic QML and chip scale packaging for various markets including down-hole, aerospace, satellite and military. We combine advanced processes and product development to provide full turnkey support for prototype to volume production of flip chip and wire bond packages including single chip, multichip and SiP applications on organic substrates or ceramic substrates. By ensuring delivery of finished wafers through our relationships with silicon OCMs, and full coordination of customer BOM requirements, we offer complete supply-chain management services for micro- electronic assemblies. Micross Components can support your custom design with: Micross supplies modules and contract assembly services for multiple platforms: industrial, airborne; commercial and government satellites; • Complete turnkey product - including program missile and ordnance; C4ISR and medical. and vendor management of all elements throughout the product lifecycle • Co-development of a statement of work (SOW) Custom Multichip Packaging (MCP) is a die based system or sub-system • Co-design, starting with schematic, netlist or product definition and documentation assembled into a single package which is then mounted to the PCB. • Environmental requirements review In its simplest form factor, two or more of the same die are combined in one industry standard package that is smaller than the equivalent • Package and material selection for optimization of electrical and environmental performance, single die packages combined. This provides the user with density and thermal management, PCB second level performance two to three generations ahead of current semiconductor reliability and cost fab processes. • Qualification requirements vis-à-vis package Typically, multichip or system in a package devices are comprised of definition, electrical test and characterization expectations multiple memory die, but often include a processor, gate array, ASIC, or • Evaluation of the power requirements vs. other logic as demanded by the customers application. They can also proposed package design; analyzed in be combined with other components such as registers, clocks, sensors, conjunction with the creation of the initial layout, triggers, passives, MEMS, voltage regulators, etc. die placement and floor planning and routing • Analysis of thermal and mechanical elements • Customer defined package and pin assignments Micross serves the defense aerospace, medical, industrial and space • Obsolescence management markets with these technologies. Design, assembly and test are • Counterfeit mitigation performed in an on shore MIL-PRF-38535, MIL-PRF-38534 facility • DNA marking certified by DSCC to class V and H. • Die revision control • On shore design, assembly and test • Use of COTS standard silicon from our die distribution partners September 2013 • Revision 3.8 7725 N. Orange Blossom Trail • Orlando, FL 32810 • 407.298.7100 • [email protected] • www.micross.com Custom & Multichip Packaging Contract Manufacturing • Through-hole • PIND Pin Grid Array (PGA) • Lead failure Ceramic Dual-In-Line Package (CDIP) • Temperature cycling Zig-Zag in-line (ZIP) • Hermetic testing Metal can • Fine and gross leak test Services • SPC, technical support • Die banking and parts management • Centrifuge • Total turnkey manufacturing, full BOM • Mechanical shock and vibration management Test Facility and Quality • DMS/obsolescence mitigation • Hot probe to 150°C • DSCC QML • Die banking and diminished sources (End of Life) support. Micross die bank is equipped with Can be tooled for full functional test MIL-PRF-38534, Class H state-of-the-art climate control systems and Capacity dependent on complexity of die and (Class K in process) nitrogen-purged dry boxes. We store and handle die/wafer MIL-PRF-38535, Class Q inventory per military/industry specifications and • Full temperature upscreening MIL-PRF-38535, Class V (assembly) provide internal class A and B die inspection. Laboratory Suitability (MIL-STD-883) • Obsolete and legacy products support • Testing for memory, mixed signal, LSI, VLSI, linear, logic, ASICs, RF, and discretes • SMD, Q and M level • Flexible, personalized customer support • Custom test equipment • Certification of wafer traceability lot to Class H or Class K requirements. Engineering & Analytical Services • Test equipment Agilent 83000 • All die preparation, sample assembly, evaluation • Scanning Electron Microscopy (SEM) Mixed Signal LTX Credence D10 and test per Table C-II in-house with full • Decapsulation traceability and MIL-STD-883 DSCC Laboratory Memory test - Teradyne J937 • Demarking and ink or laser mark Certification. Teradyne A585 • NSTS 5300.4 • Lot Acceptance Testing Testronics 201 and FET9400 Linear Test Systems LTX TS80 • Capabilities for Class S manufacturing • Design of substrates, plastic/laminate or hermetic ceramic ECL test system • AS9100 Rev. C registered • Test, burn-in and qualification Delta flex pick & place handlers • Customer specific, Source Control Drawing (SCD) • Visual inspection insures defect free die products Symtek handlers - X1 & X4 Temptronics temperature forcing systems Packaging Options • Wafer probe insures post-assembly integrity (-65°C to +150°C capability) • Pick and place automation for quick and precise • Surface mount Automated Bench Test custom packaging Plastic Ball Grid Array (PBGA) • Full static/dynamic burn-in • Component evaluation and qualification Chip Scale Package (CSP) Burn-in boards • Package and sub-assembly design Convection ovens Ceramic and HiTCE Ceramic BGA • Device characterization Static and dynamic Wakefield chambers (see Table 1) • Infant mortality testing Class 100 Clean Room Ceramic Flat Pack (FP) • Sonoscan (CSAM), X-ray Ceramic Quad Flat Pack (CQFP) • Stud pull, bond pull Ceramic gull wing Plastic, Small-Outline, J-leaded (CSOJ) • Moisture resistance SOJ, QFP, and TSOP as open cavity • Steam age/solderability Plastic, Thin Quad Flat Package (TQFP) • Salt spray Ceramic Leadless Chip Carrier (CLCC) • Thermal shock/thermal analysis September 2013 • Revision 3.8 7725 N. Orange Blossom Trail • Orlando, FL 32810 • 407.298.7100 • [email protected] • www.micross.com Custom & Multichip Packaging Contract Manufacturing • Flip-chip attach assembly including flux, high accuracy placement, reflow and precision Multichip designs are assembled on an automated capillary underfill interposer or substrate to create a customized, • Mixed technology combinations of bare die and integrated product for a unique application. packaged parts enable reduced form factors and Within the multichip package, the designer cost management can utilize bare die (wire bond or flip chip), WLCSP devices or stacked die. The critical • State of the art die placement machine – placement accuracy of ± 10µm benefits of this technology include: Bonding capabilities include: gold ball, gold • Greater functionality in a faster time- AMBYX memory, large capacity ovens and aluminum wedge to-market window than could be done AEHR ovens • Auto/manual wire bonding through silicon integration or ASIC K&S and F&K Delvotec automatic wire development. Assembly bonders • Reduced cost compared to an ASIC. • 3D and advanced IC packaging equipment 0.7 to 3.0 mil aluminum ultrasonic • Increased density and performance with 0.7 to 2.0 mil gold thermosonic • Multi-chip package or monolithic reduced PCB area utilization; reduced Heavy gauge 5 to 20 mil aluminum down routing at the PCB level and • More than 10,000 sq. ft. of clean rooms reduced weight. Reduced down routing • Bond pull-destruct/non-destruct Class 100 can provide potential PCB layer reduction Class 10,000 • Hermetic seal and lower PCB costs. Gold-tin eutectic solder reflow • Die materials - Silicon, SOS, GaAs, SiC • Design optimization through use of the Parallel seam seal most cost effective silicon solutions; • Bare die on most substrates - FR4, Flex, LCP, BT, Resistance welding – TO packages assembling various semiconductor BN, Ceramic, Polyimide Glass frit seal technologies, die geometries, or silicon • Encapsulation, transfer mold, glob-top or dam from different fabs in the same multichip • Solder re-flow and fill package. • Vacuum bake • Wafer processing • Improved signal integrity from reduced Wafer thinning to .004” • Lead trim/form trace lengths. 2 Cut range up to 8” or 250mm • Reduced PCB assembly complexity and Die sorting - automatic pick and place wider pitches, leading to simplified Wafer maps converted/uploaded to ALPS for Class 3 PCB compliance. binning, sorting to gel pack, waffle pack, tape • Allows the OEM to upgrade products, and reel, or directly packaged meet tech refreshes, or pre-planned • Automatic die attach product improvements, by using die Eutectic shrinks in the same package. Epoxy • Depending on environmental Solder requirements, the MCP can be in a ceramic hermetic or plastic encapsulated packages. Typical material properties of widely used interposers for multichip packaging Thermal Dielectric Material TCE Typical Conductor Material Conductivity Constant Description -40°C 25°C 125°C W/mK 1MHz 3.2GHz