Application Note Using both Progressive Scan and Interlace Features with ZiLOG’s eZVision 300 Family AN002101-TVC0200 ZiLOG WORLDWIDE HEADQUARTERS • 910 E. HAMILTON AVENUE • CAMPBELL, CA 95008 TELEPHONE: 408.558.8500 • FAX: 408.558.8300 • HTTP://WWW.ZILOG.COM This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact ZiLOG Worldwide Headquarters 910 E. Hamilton Avenue Campbell, CA 95008 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com Information Integrity The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Any applicable source code illustrated in the document was either written by an authorized ZiLOG employee or licensed consultant. Permission to use these codes in any form, besides the intended application, must be approved through a license agreement between both parties. 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No licenses or AN002101-TVC0200 Application Note Using both Progressive Scan and Interlace Features iii Table of Contents Overview ................................................................................................... 1 Procedure .................................................................................................. 1 Converting from the Z90356 to the Z90376 for Interlaced Mode ................. 1 Enabling and using the Progressive scan feature of the Z90376 ................ 4 Summary.................................................................................................... 6 Acknowledgement: Alex Muratov, Staff Software Engineer Steve Lindt, Manager Software Development AN002101-TVC0200 Application Note Using both Progressive Scan and Interlace Features 1 Overview The Z90376 television controller with On-Screen Display (OSD) is the latest product in ZiLOGÕs eZVisionª 300 family. It is designed to allow existing Z9033x and Z90356 software to be reused with minimal modification. One of the most important enhancements from the Z90356 is the addition of Progressive Scan OSD capability. This application note describes the software modifications required on existing software to activate the chip in the original interlaced mode as well as the new progressive scan mode. The use of progressive scan television picture displays is increasing and the OSD must be able to support these progressive scan displays. In a typical NTSC interlaced display, each HSYNC scan line is 63.5 µSec in duration. This number is derived by halving the 525 scan lines displayed every 1/60 of a second. 1 1 --- × ---------= 63.5µsec 60 262.5 In a progressive scan television display, all 525 scan lines are displayed every 1/60 of a second. Therefore each HSYNC scan line is only 31.75 µSec in duration. 1 1 --- × ----= 31.75µsec 60 525 For detailed information about how the hardware for the Z90376 TV controller with OSD supports progressive scan applications, please refer to the product specification PS005600-TVC1299. Procedure Converting from the Z90356 to the Z90376 for Interlaced Mode When adding new features to the Z90376, some unused control registers bits were defined with new functions. These registers must be properly configured to allow existing as well as new code to be used. The following modifications must be made for interlace software to operate correctly: AN002101-TVC0200 Application Note Using both Progressive Scan and Interlace Features 2 1. The Z90376 has a new bit control for switching between interlaced and progressive scan. The Z90376 power up resets to progressive scan. Therefore Register 1 Bank 1 bit 14 must be set to a 1 for Interlaced Mode. 2. In the VSYNC interrupt service routine (ISR), the Speed Control Register (Register 1, Bank 1) must be programmed correctly. Refer toTable 1 for detailed bit descriptions. LD SR, #%0020 ;switch to bank 1 registers LD SCLK_FREQ, #(INTERLACED|%0A00|FRAME_START| DOUBLE_RGB|VLO_ENABLE|FAST_CLK) INTERLACED EQU %4000 FRAME_START EQU %0020 DOUBLE_RGB EQU %0004 VCO_ENABLE EQU %0002 FAST_CLK EQU %0001 3. The OSD vertical starting position, on a scan line by scan line basis, might not be the same in the Z90356 as in the Z90376 because of scan line buffers. Adjust the position if necessary. 4. The OSD horizontal starting point control is not the same in the Z90356 as in the Z90376. The horizontal shift field of Register 1 Bank 1(bits 13-8) must be used to define the horizontal starting position of the OSD. Note that the old Horizontal start position (Register 6, Bank 1, bits 0:3) are all set high (0xF). This is very important. Valid delays from 0x1 to 0xF were allowed in previous Z893xx/Z903xx controller models. It must be set to F in the Z90376 controller when an OSD scan line is displayed. 5. The OSD buffer must be flushed (transparent blanks) at the end of the visible display to avoid continuous repeat of the last two scan lines of the OSD. 6. All VCO clock switching must be removed from any existing Z893xx/Z903xx software (Register 6, Bank 1, bit 4 = 1). Refer to the Z90371/76 product specification for more information. AN002101-TVC0200 Application Note Using both Progressive Scan and Interlace Features 3 Table 1 R1(1) Speed Control Register Reg field Bit position R W Data Description Reserved f--------------- Reserved Scan mode -e-------------- RW 1 Standard interlaced mode 0 Progressive scan mode Ð POR H_SHIFT --dcba98-------- R W %D Shift right in 4 pixels increment POR = 0 1xHSYNC --------7------- RW 1 1xHSYNC is connected to Port03 0 1xHSYNC is 2x HSYNC/2 - POR Skip_hsync ---------6------ N/ W1Skip next 2x HSYNC A 0 Do not skip next 2x HSYNC Frame_start ----------5----- N/ W1Field start initialization A 0 No effect OSD_black -----------4---- RW 1 Next output line is OSD 0 Next output line is black Line_buffer_mode ------------3--- RW 1 Interlaced (OSD/black) 0 Progressive (OSD/OSD) Ð POR 2x_RGB -------------2-- RW 1 Double RGB output 0 Normal RGB output - POR Fast_enable --------------1- R W 1 PVCO/SVCO enabled 0 PVCO/SVCO disabled - POR Fast_slow ---------------0 R W 1 SCLK is 12.058 MHz 0 SCLK is 32.768 KHz - POR Note: Italic entries are unchanged from previous 3xx revisions. AN002101-TVC0200 Application Note Using both Progressive Scan and Interlace Features 4 Enabling and using the Progressive scan feature of the Z90376 The following changes and additions must be implemented to support progressive scan OSD in the Z90376: 1. All VCO clock switching must be removed from any existing Z893xx/Z903xx software. Clock switching in the Z893xx/Z903xx hardware allows the OSDÕs leading edge to be locked to the video pictureÕs HSYNC. This creates a stable jitter-free picture. Two changes are required to allow clock switching to operate properly. The first change is that clock switching must be disabled by setting bit 4 of Register 6, Bank 1 to 1. When clock switching is enabled, the receipt of an HSYNC automatically switches the clock from the primary VCO (PVCO) to the secondary VCO (SVCO or on-screen display VCO). The second change is that before returning back from the HSYNC interrupt service routine (ISR), software must reset the clock back to the PVCO by setting a hardware register. The following code turns off VCO clock switching in the Z90376: LD SR, #%0020 ;switch to bank 1 registers LD EXT6, #%001F ;Register 6, Bank 1, bit 4 = 1 Note that the Horizontal delay position (Register 6, Bank 1, bits 0:3) are all set high (0xF). This is very important. Valid delays from 0x1 to 0xF were allowed in previous Z893xx/Z903xx controller models. It must be set to F in the Z90376 controller when an OSD scan line is displayed. The following code (or something similar to it) must be removed from the end of the HSYNC ISR that switches the clock from SVCO back to PVCO. LD SR, #%0020 ;switch to bank 1 registers LD A, EXT6 AND A, #%000F ;clear all bits except the horizontal delay position OR A, #%0020 ;reset the clock back to PVO LD EXT6, A The preceding code MUST be removed to use the Z90376. AN002101-TVC0200 Application Note Using both Progressive Scan and Interlace Features 5 2. For every VSYNC, the character size must be reset to 1X character size. Subsequent row drivers which run in the HSYNC can set the character size on a scan line by scan line basis. This is controlled in Bank 3, register 4, bits 5 and 6. LD SR, #%0060 ;switch to bank 3 registers LD A, EXT4 AND A, #%FF80 ;set character size to 1X, ;set CGROM scan line to 0 LD EXT4, A 3. The Speed Control Register (Register 1, Bank 1) must be programmed within the VSYNC interrupt service routine (ISR). The field start initialization bit (Frame_start) must be flipped within each VSYNC ISR to display the OSD correctly. This is accomplished by writing a Ò1Ó into bit 5 of Register 1, Bank 1 every VSYNC. Refer to Table 1 for bit descriptions for the Register 1 Bank 1 speed control register. The following data are written into Register 1, bank 1 every VSYNC: LD SR, #%0020 ;switch to bank 1 registers LD SCLK_FREQ, #(PROGRESSIVE|%0A00|FRAME_START| DOUBLE_RGB|VCO_ENABLE|FAST_CLK) PROGRESSIVE EQU %0000 FRAME_START EQU %0020 DOUBLE_RGB EQU %0004 VCO_ENABLE EQU %0002 FAST_CLK EQU %0001 Please refer to the Z90371/376/379 product specifications for more information.