ComparisonbetweenCISCandRISC YiGao,ShilangTang,ZhongliDing {ygao1,stang2,zding1}@cs.umbc.edu ABSTRACT PerformancecomparisonbetweenRISC(ReducedInstructionSetComputer)andCISC (ComplexInstructionSetComputer)isaquitepopulartopic,andmanyconclusionsaremadein previouswork.Thispapercomparesthesetwodifferentarchitecturesinacomprehensiveway, trytocapturethepurelyarchitecturaladvantagesofRISCandCISC,andthedevelopmenttrends ofthefuturearchitectures.Ourcomparisonisnotonlybasedontheoreticalpointofview,but alsobasedonexperimentalresultstosupportourconclusions.WechooseMIPSR2000(RISC) andIntel80386(CISC)asthecomparisonmicroprocessors,wecomparethemonseveralinteger andfloating-pointbenchmarkstoverifyanddrawconclusions. 1.Introduction RISCandCISCstandfortwodifferentcompetingphilosophiesindesigningmoderncomputer architecture.Thedebatebetweenthemhasbeengoingonforalongtimeandwilllikely continue.ThedifferencebetweenRISCandCISCcanlaysonmanylevels,lotsofplausible argumentsareputforwardbybothsides,suchascodedensity,transistorcounts,memory bottlenecks,compileranddecodecomplexityetc.Thispaperintendstocomparethesetwo differentideasindetail,theirdistinctcharacters,theirpossiblespecificapplicationdomains,their currentscopeandtheirfuturedevelopmenttotheCPUdesign. TheexperimentismainlybasedontheMIPSR2000andIntel80386instructionsets,MIPS R2000isatypicalproductofpureRISCwhileIntel80386isatypicalkindofpureCISCchip. Theyappearedalmostatthesametime(mid80's),also,theyareboth32-bitprocessors,sowe choosethemasourtargets.Weselectaseriesofintegerandfloat-pointingbenchmarks,use sometracingtoolsandmakesomestatisticstomakeaseriesofcomparisonsbetweenthesetwo instructionsets. InSection2,wewillpresentsomebasicknowledgeaboutRISCandCISC,theevolutionhistory fromCISCtoRISC,andthebasicdifferencebetweenthem.InSection3,wepresenta comparisonbetweentwokindsofchips:MIPSR2000andIntel80386,andobtainsome meaningfulstatisticalresults,basedontheseresults,wemakesomeconclusions.Finally,in Section4,wewillhavesomediscussionandfigureoutwhowinsinthisbattleoverCISCand RISC,what’sthefuturestatus. 2.Background 2.1History TheIBM360system,createdin1964,wasprobablythefirstmodernprocessorsystem,which initiatedtheideaofcomputerarchitectureincomputerscienceandadoptedmicro-codedcontrol. Micro-codedcontrolfacilitatedtheuseofcomplexinstructionsetsandprovidedflexibility,thus appearedso-calledComplexInstructionSetComputer(CISC).CISCwasprimarilymotivatedby adesiretoreducethe"semanticgap"betweenthemachinelanguageoftheprocessorandthe high-levellanguagesinwhichpeoplewereprogramming,thetheorywasthatsuchaprocessor wouldhavetoexecutefewerinstructionsandthuswouldhavebetterperformance.[2]Also,at thatera,hardwarewasextremelyexpensive,thusfewermemoryoccupywasstronglypreferred. Ontheotherhand,thecompilertechnologyatthattimewasinitsinfancy,sameasadvanced programminglanguage,peoplealwaysusedassemblylanguageatthattime,thus,suchadesign asCISCmadepeoplenoneedconsidertheinfluenceofcompilertoCPUperformance. CISCcomputersarebasedonacomplexinstructionsetinwhichinstructionsareexecutedby microcode.Microcodeallowsdeveloperstochangehardwaredesignsandstillmaintain backwardcompatibilitywithinstructionsforearliercomputersbychangingonlythemicrocode, thusmakeacomplexinstructionsetpossibleandflexible.AlthoughCISCdesignsallowalotof hardwareflexibility,thesupportingofmicrocodeslowsmicroprocessorperformancebecauseof thenumberofoperationsthatmustbeperformedtoexecuteeachCISCinstruction.ACISC instructionsettypicallyincludesmanyinstructionswithdifferentsizesandexecutioncycles, whichmakesCISCinstructionshardertopipeline. Fromthe60'sCISCmicroprocessorsbecameprevalent,eachsuccessiveprocessorhavingmore andmorecomplicatedhardwareandmoreandmorecomplexinstructionsets.Thistrendstill continuestodayfromIntel80486,PentiumMMXtoPentiumIII. However,inthemiddleof70's,peoplebegantodoubtthedesignphilosophybehindCISC.With moreandmorecomplexinstructionssets,decodingandexecutionofsuchinstructionswere complicatedandtime-consuming,also,theexpensiveoverheadbroughtbythemsloweddown theexecutionofthosemorefrequentlyusedsimpleinstructions.Moreover,withthedevelopment ofhigh-levellanguages,makinggooduseoftheinstructionsetposedaproblemtocompilers, peoplerecognizedthatcompilerswereunabletotakeadvantageofthecomplexinstructionsets. Allthesemayfinallydecreasetheperformance.Ontheotherhand,withthedecliningcostof memorydevicesandimprovedcompilertechnology,itmaybefeasibletoconsidersimplifying theinstructionsetwiththecostoflargercodesizeandhighermemorybandwidthrequirements. Basedonaboveobservation,RISC(ReducedInstructionSetComputer)chipsevolvedaround themid-1970asareactionatCISCchips.In70's,JohnCockeatIBM'sT.JWatsonResearch CenterprovidedthefundamentalconceptsofRISC,theideacamefromtheIBM801 minicomputerbuiltin1971whichisusedasafastcontrollerinaverylargetelephoneswitching system.ThischipcontainedmanytraitsalaterRISCchipshouldhave:fewinstructions,fix- sizedinstructionsinafixedformat,executiononasinglecycleofaprocessorandaLoad/Store architecture.[3]TheseideaswerefurtherrefinedandarticulatedbyagroupatUniversityOf CaliforniaBerkeleyledbyDavidPatterson,whocoinedtheterm"RISC".[4]Theyrealizedthat RISCpromisedhigherperformance,lesscostandfasterdesigntime. ThedesignphilosophiesbehindRISCchipare"makecommoncasefaster"and"simpleisbest", whicharebasedonthepremisethat20%ofacomputer'sinstructionsdo80%ofthework.Ina CISCchip,manyverycomplexinstructionsneverorseldomused,buttheymakethecontrolunit extremelycomplexandthushaveahighcontrolunitdelay.ARISCinstructionsetincludes fewerandsimplerinstructionswithhard-wiredcontrol,simplerprocessorpipeline,alarger numberofregisters,asmallertransistorcountwhichmakesiteasiertodesignandcheaperto produce,andahigherclockrateetc.Sincefewerinstructionsexist,it'salsoeasiertowrite powerfuloptimizedcompilers.Also,withsimplerandfixed-sizeinstructionsandhardware decoding,furtherperformanceimprovementsuchassuperscalarandspeculationispossible easier. AsresearcherscontinuedintoRISCduringthe1970'sand1980'sitbecameclearthatthefactors describedaboveresultedinaspeedincreaseoverCISCdesigns. However,withthefleetingoftime,thebattleoverRISCandCISCbecameblur,thoughpure RISCmachinemayoutperformpureCISCmachine,butbothofeachhavesomebadfaceswhich interferetheirfurtherimprovementofperformance.In90's,thetrendismigratingtowardeach other,RISCmachinesmayadoptsometraitsfromCISC,whileCISCmayalsodoitviceversa. AnexampleisIntelmicroprocessors,thoughtheyuseaCISCinstructionsetandareconsidered CISCchips,theinternalarchitecturehasgraduallymigratedtoRISC.Beginningwiththe PentiumPro,IntelusedaRISCcore,convertingCISCinstructionstoRISC-likeinstructionsthat Intelcallsmicro-ops(Figure2.1).Themicro-opsovercomemuchofthespeedpenaltyofCISC architecturebyconvertingallinstructionstothesamelengthbeforetheyareprocessed.Micro- opsalsoeliminatearithmeticoperationsthatdirectlychangememorybyloadingmemorydata intoregistersbeforeprocessing.Also,Pentiumiscompatiblewith80486andoutperformRISC machineinperformancebyadoptingsuperscalarandpipelinestructure.Withtheadditionof RISCcoretechnology,MMX,andSSE,CISCperformancehasbecomeverycompetitivewith thatofRISCcomputers. Figure2.1 Anotherimportantthingwewanttomentionhereisthatalthoughasignificantnumberof microprocessorsarebasedonRISCtechnologytoday,RISCneverachievedthemarket penetrationthatitsearlyproponentshopedfor.Inpart,thislimitedacceptancewasbecausethe performanceimprovementofferedbyRISCwasoffsettedbyaverylargeinstalledbaseofx86- compatibleCISCcomputers.WithlargeinvestmentsinsoftwareforCISCcomputers, corporationdecision-makerscouldnotjustifyswitchingtoRISCinmanycases. Inthesection2.2weprovideasimplecomparisonbetweenCISCandRISCthatisbasedonthe architectureitself. 2.2RISCversusCISC ACISCprocessorhasmostofthefollowingproperties: • Richerinstructionset,somesimple,someverycomplex • Instructionsgenerallytakemorethan1clocktoexecute • Instructionsofavariablesize • Instructionsinterfacewithmemoryinmultiplemechanismswithcomplexaddressing modes • Nopipelining • Upwardcompatibilitywithinafamily • Microcodecontrol • Workwellwithsimplercompiler Astimepassed,oneofthenon-RISCarchitecturewithlargemarketistheIntelx86family,ithas somespecificcharacteristicsbecameassociatedwithCISC: • Segmentedmemorymodel • Fewregisters • Crappyfloatingpointperformance TypicallyCISCchipshavealargeamountofdifferentandcomplexinstructions.Itbelievesthat hardwareisalwaysfasterthansoftware;thereforeoneshouldmakeapowerfulinstructionset, whichprovidesprogrammerswithassemblyinstructionstodoalotwithshortprograms.In commonCISCchipsarerelativelyslowperinstructioncomparedtoRISCchips,butuseless instructionsthanRISC. MostactualRISCmachinessuchastheRISCIandRISCIIfromtheUniversityofCaliforniaat BerkeleyandtheMIPSfromStanfordUniversityhavemostofthefollowingcommon properties:[6][9] • Simpleprimitiveinstructionsandaddressingmodes • Instructionsexecuteinoneclockcycle • Uniformedlengthinstructionsandfixedinstructionformat • Instructionsinterfacewithmemoryviafixedmechanisms(load/store) • Pipelining • Instructionsetisorthogonal(littleoverlappingofinstructionfunctionality) • Hardwiredcontrol • Complexitypushedtothecompiler Also,moreideasaddedtonewRISCtechnology,including: • Superscalarandout-of-orderexecution • Largenumberofregisters • Fastfloatingpointperformance TheessenceofRISCarchitectureisthatitallowstheexecutionofmoreoperationsinparallel andatahigherratethanpossiblewithaCISCarchitectureemployingsimilarimplementation complexity.Itcannotonlyimproveparallelismbypipelining,butalsomakesuperscalarandout- of-orderexecutionpossible. Backinthemiddletolate80's,thebattleoverRISCandCISCismainlynon-IntelversusIntel x86,andRISCseemedtohaveaclearlyupside,untiltheappearingofi486,Pentiumandnow