DSTni-LX Data Book Revision F Part Number GC-900-252 Copyright and Trademark © 2003 Grid Connect, Inc. All rights reserved. No part of this manual may be reproduced or transmitted in any form for any purpose other than the purchaser's personal use, without the express written permission of Grid Connect, Inc. Grid Connect, Inc. has made every effort to provide completeness and accuracy of this material, but makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose. In no event shall Grid Connect, Inc. be liable for any incidental, special, indirect, or consequential damages whatsoever included but not limited to lost profits arising out of errors or omissions in this manual or the information contained herein. Grid Connect, Inc. products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of a Grid Connect, Inc. product could create a situation where personal injury, death, or severe property or environmental damage may occur. Grid Connect, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Grid Connect and the Grid Connect logo, and combinations thereof are registered trademarks of Grid Connect, Inc. DSTni is a registered trademark of Lantronix, Inc. Ethernet is a registered trademark of Xerox Corporation. Am186 is a trademark of Advanced Micro Devices, Inc. DataFlash® is a registered trademark of Atmel Corporation. BasicCAN and PeliCAN are registered trademarks of Phillips Semiconductors. SPI is a trademark of Motorola, Inc. All other product names, company names, logos or other designations mentioned herein are trademarks of their respective owners. Grid Connect 1630 W. Diehl Rd. Naperville, IL 60563 Phone: 630.245.1445 Technical Support Phone: 630.245.1445 Fax: 630.245.1717 On-line: www.gridconnect.com Revision Date Author Comments A 08-28-01 GR Initial Release B 09-30-01 AC Cosmetic changes and copyright page. C 10-15-01 AC Removed Glossary and Index, edited block diagram, Baud Rate table and made cosmetic changes throughout. D 11-27-01 GR Replaced Index. Revised format. E 2-18-02 GR Ready is synchronous. 12/14/2005 Last edited and saved. New Format 1:58 PM F 12-14-05 GR Revised tables. Added notes Table of Contents 1 Introduction 1 1.1 Purpose of This Manual ..............................................................................................................1 1.2 Manual Overview........................................................................................................................1 1.3 General Description.....................................................................................................................2 1.4 Key Features & Benefits .............................................................................................................3 1.5 Hardware Description .................................................................................................................3 1.5.1 High Performance 16-Bit Microprocessor ........................................................................3 1.5.2 Programmable Timers.......................................................................................................4 1.5.3 Asynchronous Serial Ports ................................................................................................5 1.5.4 Interrupt Controller ...........................................................................................................5 1.5.5 SPI Controller ...................................................................................................................5 1.5.6 Hardware Watchdog Timer...............................................................................................5 1.5.7 10/100 Mbps Ethernet Controller......................................................................................5 1.5.8 Static RAM .......................................................................................................................5 1.5.9 Profibus DP Master/Slave Controller................................................................................5 1.5.10 Boot ROM Memory ........................................................................................................6 1.5.11 Dual Port Memory Shares 32 I/O Pins............................................................................6 1.5.12 Dual 1 Mbps CAN Controllers........................................................................................6 1.6 Communication Protocols...........................................................................................................6 1.6.1 CAN ..................................................................................................................................6 1.6.2 Profibus.............................................................................................................................8 1.6.3 Ethernet.............................................................................................................................8 1.7 Development Tools .....................................................................................................................9 1.7.1 Paradigm ...........................................................................................................................9 2 1.7.2 FS ICE .............................................................................................................................9 1.7.3 Developers Evaluation Kits...............................................................................................9 1.8 System Diagram........................................................................................................................10 1.8.1 DSTni-LX Block Diagram..............................................................................................10 1.9 Programming.............................................................................................................................12 1.10 System Overview ....................................................................................................................12 1.10.1 DSTni-LX Package Options..........................................................................................12 1.10.2 DSTni-LX 160-Pin Package .........................................................................................13 1.10.3 Pin Descriptions ............................................................................................................14 1.10.4 Pin Out Table ................................................................................................................25 1.10.5 48 MHz Clock...............................................................................................................28 1.10.6 20/24-Bit Address Support............................................................................................29 DSTni-LX Data Book Table of Contents • i 2 Peripheral Control Block 31 2.1 Memory Layout.........................................................................................................................31 2.2 Peripheral Registers...................................................................................................................32 2.2.1 PCB Relocation Register (RELREG, Offset = FEh).......................................................33 2.2.2 Processor Release Level Register (PRL, Offset = F4h) ..................................................33 2.2.3 System Configuration Register (SYSCON, Offset = F0h)..............................................33 2.2.4 Auxiliary Configuration Register(AUXCON, Offset = F2h)..........................................34 2.2.5 Chip Select ......................................................................................................................34 2.2.6 Ready and Wait-State Programming...............................................................................35 2.2.7 Upper Memory Chip Select Register (UMCS, Offset = A0h).........................................36 2.2.8 Lower Memory Chip Select (LMCS, Offset = A2h)) .....................................................37 2.2.9 Middle Memory Chip Select (MMCS, Offset = A6h).....................................................37 2.2.10 Memory / Peripheral Control Select (MPCS, Offset = A8h).........................................38 2.2.11 Peripheral Chip Selects (PACS, Offset = A4h).............................................................39 2.2.12 Dual Port Memory Select (DPMS, Offset = AAh)........................................................39 2.2.13 Chip Select Assignments...............................................................................................40 2.3 Timers .......................................................................................................................................41 2.3.1 Timer Registers ...............................................................................................................41 2.3.2 Basic Timer Operation ....................................................................................................42 2.3.3 Timer 0 and Timer 1 Control (T0CON, offset 56h; T1CON, offset 5Eh).......................42 2.3.4 Timer 2 Control (T2CON, offset 66h) ............................................................................43