NDA KSZ8342Q under Data Sheet Version 1.0 / February 5, 2014 provided © Micrel, Inc. 2013, 2014 All rights reserved Micrel is a registered trademark of Micrel and its subsidiaries in the United States and certain other countries. All other trademarks are the property of their respective owners. The information furnished by Micrel in this document is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devicesconfidential or systems that (a) are intended for surgic al implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. Micrel Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 1/94 Table of Contents 1 General Description .................................................................................................................................... 8 2 Features ...................................................................................................................................................... 9 3 Applications .............................................................................................................................................. 11 4 Part Ordering Information ......................................................................................................................... 12 5 Package Pinout ......................................................................................................................................... 13 6 Pin Descriptions and Strapping Options ...................................................................................................NDA 14 7 System Memory Map ................................................................................................................................ 20 8 MIPS Processor Core ............................................................................................................................... 21 8.1 Execution Units .................................................................................................................................. 22 8.2 Multiply/Divide Unit (MDU) ................................................................................................................ 22 8.3 System Coprocessor ............................................................................................................under ............. 22 8.4 Memory Management Unit ................................................................................................................ 23 8.5 Translation Lookaside Buffer ............................................................................................................. 23 8.5.1 Joint TLB ................................................................................................................................... 23 8.5.2 Instruction TLB .......................................................................................................................... 23 8.6 Cache Controller................................................................................................................................ 24 8.7 Enhanced JTAG (EJTAG) .........................................................................................................provided ........ 24 8.8 Power Management .......................................................................................................................... 24 9 ZSP Voice Module Processor ................................................................................................................... 26 9.1 ZSP Architecture ............................................................................................................................... 26 9.2 8.2 ZSP Functional Units ................................................................................................................... 26 9.2.1 Instruction Unit ........................................................................................................................... 27 9.2.2 Data Unit .................................................................................................................................... 27 9.2.3 Pipeline Control Unit .................................................................................................................. 28 9.2.4 Execution Units .......................................................................................................................... 28 9.2.5 Registerconfidential Files ............................................................................................................................. 28 9.2.6 Device Emulation Unit ............................................................................................................... 28 9.3 ZSP Boot Process ............................................................................................................................. 28 10 3-Port Switch ............................................................................................................................................ 29 10.1 Media Access Controller (MAC) ........................................................................................................ 30 Micrel10.1.1 Address Lookup ......................................................................................................................... 30 Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 2/94 10.1.2 Learning ..................................................................................................................................... 30 10.1.3 Migration .................................................................................................................................... 30 10.1.4 Aging ......................................................................................................................................... 31 10.1.5 Forwarding ................................................................................................................................. 31 10.1.6 MAC Operation .......................................................................................................................... 34 10.2 Physical Layer (PHY) ........................................................................................................................ 36 10.2.1 100BASE-T Transmit................................................................................................................. 37 10.2.2 100BASE-T Receive.................................................................................................................. 37 10.2.3 10BASE-T Transmit..............................................................................................................NDA..... 38 10.2.4 10BASE-T Receive.................................................................................................................... 38 10.2.5 MDI/MDI-X Auto Crossover ....................................................................................................... 39 10.2.6 Auto-Negotiation ........................................................................................................................ 39 10.2.7 PHY Power Management ..........................................................................................................under 40 10.3 Advanced Switch Functions .............................................................................................................. 42 10.3.1 Bypass Mode ............................................................................................................................. 42 10.3.2 IEEE 802.1Q VLAN Support ..................................................................................................... 42 10.4 3-Port Switch QoS Priority Support ................................................................................................... 43 10.4.1 Port-Based Priority .................................................................................................................... 43 10.4.2 802.1p-Based Priority ................................................................................................................ 43 10.4.3 DiffServ-Based Priority .......................................................................................................provided ....... 44 10.4.4 Spanning Tree Support ............................................................................................................. 44 10.4.5 Rapid Spanning Tree Support ................................................................................................... 45 10.4.6 Tail Tagging Mode ..................................................................................................................... 47 10.4.7 IGMP Support ...........................................................................................................................