LOW-POWER MULTI-GHZ SIGE FPGAS FOR RECONFIGURABLE COMPUTING By Kuan Zhou A Thesis Submitted to the Graduate Faculty of Rensselaer Polytechnic Institute in Partial Fulfillment of the Requirements for the Degree of DOCTOR OF PHILOSOPHY Approved by the Examining Committee: John F. McDonald, Thesis Adviser Toh-Ming Lu, Member Yannick L. Le Coz, Member Tong Zhang, Member Rensselaer Polytechnic Institute Troy, New York July 2004 (For Graduation 2004) LOW-POWER MULTI-GHZ SIGE FPGAS FOR RECONFIGURABLE COMPUTING By Kuan Zhou An Abstract of a Thesis Submitted to the Graduate Faculty of Rensselaer Polytechnic Institute in Partial Fulfillment of the Requirements for the Degree of DOCTOR OF PHILOSOPHY Major Subject: Electrical, Computer and Systems Engineering The original of the complete thesis is on file in the Rensselaer Polytechnic Institute Library Examining Committee: John F. McDonald, Thesis Adviser Toh-Ming Lu, Member Yannick L. Le Coz, Member Tong Zhang, Member Rensselaer Polytechnic Institute Troy, New York July 2004 (For Graduation 2004) c Copyright 2004 by Kuan Zhou All Rights Reserved ii CONTENTS LISTOFTABLES .................................viii LISTOFFIGURES ................................ x ACKNOWLEDGMENT ..............................xvi ABSTRACT ....................................xvii 1. Introduction................................... 1 1.1 Motivation................................. 2 1.1.1 Current Commercial CMOS FPGAs . 2 1.1.2 HighSpeedApplications . 4 1.1.3 FPGAMigrationtoASICs. 4 1.2 ResearchGoals .............................. 5 1.3 ThesisOutline............................... 6 2. FieldProgrammableGateArrays . 7 2.1 LogicBlockArchitecture . 7 2.2 ProgrammingTechnology . 8 2.2.1 Antifuse .............................. 10 2.2.2 EPROM,EEPROMandFlash. 11 2.3 Configware................................. 12 2.4 ComputingPlatforms. 13 2.4.1 ACM................................ 13 2.4.2 SPLASH-2............................. 14 2.4.3 DISC................................ 15 2.4.4 MATRIX ............................. 16 3. Xilinx6200architecture . 17 3.1 TheEarlyYears.............................. 17 3.2 ConfigurableLogicBlock. 18 3.3 RoutingResources ............................ 20 3.4 FastMapTM ................................ 22 3.5 ControlRegisters ............................. 23 iii 3.6 PartialReconfiguration. 24 3.7 DesignConsiderations . 26 4. SiliconGermaniumTechnology . 28 4.1 TheHistoricalReview .......................... 28 4.2 StateoftheArt.............................. 29 4.3 WhichOneisBetter: Si,SiGeorIII-V? . 30 4.4 SiGeHBTDevices ............................ 32 4.4.1 DeviceStructureandProcessSteps . 32 4.4.2 BandDiagrams .......................... 33 4.5 AdvantagesofSiGeHBTs . 34 4.5.1 β inSiGeDevices......................... 34 4.5.2 CutoffFrequency ......................... 35 4.5.3 EarlyEffect ............................ 36 4.5.4 Cryogenic Operation . 37 4.5.5 SiGeHBT+SiCMOS=SiGeBiCMOS . 37 4.6 BreakdownVoltages ........................... 37 4.6.1 BVCBO ............................... 38 4.6.2 BVCEO ............................... 38 4.6.3 BVCES and BVCER ........................ 39 4.6.4 Conclusion............................. 39 5. ECLandCMLcircuitdesign. 41 5.1 EmitterCoupledLogic . 41 5.2 CMLDesignEquations. 42 5.3 TheDifferentialNature. 44 5.4 DCAnalysis................................ 45 5.5 Comparison with Other Logic Families . 48 6. SiGeFPGADesignTechniques . 51 6.1 PowerAnalysis .............................. 51 6.2 LowSignalSwing............................. 52 6.3 Simplified Interface between SRAMs and CML . 55 6.4 Modification of the Configurable Logic Block . 58 6.5 PowerControlCircuits(SiGe5HP) . 59 iv 6.5.1 Circuit Topology . 59 6.5.2 MeasuredResults......................... 62 6.6 ConfigurationMemory . 65 6.7 X-patternDecoding............................ 66 6.8 Miscellaneous ............................... 67 6.8.1 Programmable Interconnects . 67 6.8.2 CurrentMirror .......................... 71 6.9 Conclusion................................. 73 7. SiGeFPGAApplications. 74 7.1 FIRDesign ................................ 75 7.2 1:16DEMUX ............................... 80 7.2.1 Implementation . 82 7.2.2 SecondDesign........................... 85 7.3 FFT .................................... 86 7.3.1 The Cooley-Tukey FFT Algorithm . 87 7.3.2 Radix-2 Cooley-Tukey Algorithm Implementation . 88 7.3.3 Adderimplementation . 90 7.3.4 Twiddlefactor .......................... 91 7.3.4.1 Conventional implementation [100] . 91 7.3.4.2 Multiplier implementation in FPGAs . 93 7.3.5 LargeFFT............................. 94 7.3.6 Implementation . 95 7.4 Conclusion................................. 95 8. Deep Trench Isolation Sharing Techniques . 97 8.1 DTISharingMethodI .......................... 98 8.2 DTISharingMethodII. 99 8.3 DTISharingMethodIII . .100 8.4 DTISharingMethodIV . .101 8.5 ExperimentalResults. .101 8.5.1 XC6200 CLB Combinational Path Delay . 102 8.5.2 XC6200 CLB Sequential Path Delay . 108 8.5.3 1-bit Bit-level Pipelined Adder . 110 v 9. TestPlanandResults .............................114 9.1 ComponentDesign ............................114 9.1.1 Pad Driver Design . 114 9.1.2 Voltage-Controlled Oscillator Design . 116 9.1.2.1 Tunable Range . 116 9.1.2.2 VCO Implementation . 118 9.1.3 Power Rail Droop . 119 9.2 TestSetup ................................120 9.2.1 Tektronix 11801C Digital Sampling Oscilloscope . 120 9.2.2 SignalGenerator . .121 9.2.3 GGB Industries Inc. Picoprober ................122 9.3 MeasurementExamples. .123 9.3.1 FirstChip.............................123 9.3.2 SecondChip............................125 9.3.2.1 Measured Data . 125 9.3.3 TheAdderDesign ........................129 9.3.3.1 Simulation and Measurement . 130 10.The8HPSiGeFPGA..............................133 10.1The8HPSiGeCLB............................133 10.1.1 DTI Techniques in 8HP . 134 10.1.2 Programming Techniques . 135 10.1.2.1 Serial Programming . 137 10.1.2.2 Random Access Programming . 138 10.1.2.3 Serial Programming Versus Random Access Program- ming...........................138 10.1.3 Layout Arrangement . 141 10.2 The 48 488HPFPGA.........................142 × 10.2.1 Power Consumption . 143 10.2.2 ThePinArrangement . .143 10.2.3 Connecting the A/D Converters . 145 10.3Conclusion.................................146 11.Summary and Directions for Future Research . 147 11.1Summary .................................147 11.1.1 SiGeProcessandCML. .147 vi 11.1.2 Reduction of Power in SiGe FPGA . 148 11.1.3 Deep Trench Sharing Techniques . 148 11.1.4 High Speed Applications . 149 11.2 DirectionsforFutureWork. 149 11.2.1 Bit-SerialCLBs . .150 11.2.2 AsynchronousFPGAs . .151 LITERATURECITED ..............................153 APPENDICES A. Unity-gain points of a bipolar differential pair [85] . ........162 B. 48 48SiGeFPGA ...............................164 × B.1 ChipLayout................................164 B.2 PadArrangement.............................165 B.3 PinList ..................................166 C.VelabHDLmodel................................169 C.1 4-bitAdder ................................169 C.2 Multiplier .................................172 vii LIST OF TABLES 1.1 Top 7 FPGA manufacturers in 2002 (total of $2.3 billion) (after [2]). 3 2.1 FPGAsandlogicunitgranularity. 9 2.2 Virtex-II Field-Programmable Gate Array Family Members [12]. 9 2.3 Stratix II Family Highlights [13]. ... 9 2.4 Programming Technology of FPGAs [14]. 10 3.1 Summaryofdevicefeatures[39]. 17 3.2 CALProgrammingTable[40]. 19 3.3 Maximum Number of Column Wildcards [41]. 25 4.1 Key Steps in the Evolution of SiGe HBT Technology [42]. ..... 28 4.2 Relative Performance Comparisons of Various Device Technologies for RFICs (Excellent: ++; Very Good: +; Good: 0; Fair: ; Poor: ). 31 − −− 4.3 Representative SiGe HBT Parameters for Three Distinct SiGe HBT BiCMOS Technology Generations (after [42]). 33 5.1 Logic gates comparison [89]. 49 6.1 SiGe HBT CLB performance with all trees on. 63 6.2 Comparison of the numbers of local and non-local routing resources for the critical paths in different applications (The figures on the left of the “/” are based on the original internet topology while the ones on the rightarebasedonthenewtopology). 71 7.1 Transition between X3−0 and M3−0 (X0=N0,X1=Z0,X2=Y0,X3=K0). 77 7.2 ContentsoftheLUT. ............................ 79 7.3 Comparison of two implementations. 86 8.1 Areasavingsinfourdifferentmethods. 102 8.2 Layoutsizecomparison.. .102 8.3 Chipspecifications. .............................105 8.4 Data of simulation and measurement (IBM 7HP design kit V1.2.2.0). 106 viii 8.5 Chipspecifications. .............................112 9.1 FFIVCOfrequencyrange. .119 9.2 Data of simulation and measurement (IBM 7HP design kit V1.2.2.0). 124 9.3 Data of simulation and measurement (IBM 7HP design kit V1.2.2.0). 127 10.1 Area savings using four DTI sharing techniques in SiGe 8HP (the con- ventional four HBT layout size is 13.88 µm 8.6 µm). .........134 × B.1 PinList. ...................................168 ix LIST OF FIGURES 1.1 Makimoto’sWave[1]. ............................ 1 2.1 ConventionalFPGAstructure. 7 2.2 PLICEantifusestructure[18]. 11 2.3 Flashswitch[22]. .............................. 11 2.4 Fournodecluster[30]. ........................... 13 2.5 DISC system organization [37]. 15 3.1 FunctionUnit[40]. ............................. 18 3.2 CellRouting[40]. .............................. 19 3.3 Functionalunit[41].............................. 20 3.4 Basiccellstructure[41].. 21 3.5 XC6200routingstructure. 22 3.6 Configuration