A CMOS Digital Beamforming Receiver by Sunmin Jang A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Electrical Engineering) in the University of Michigan 2018 Doctoral Committee: Professor Michael P. Flynn, Chair Professor Zhong He Assistant Professor Hun-Seok Kim Associate Professor Zhengya Zhang Sunmin Jang [email protected] ORCID iD: 0000-0002-0706-9786 © Sunmin Jang 2018 Acknowledgements Over the past five years I have received lots of support and encouragement from a number of individuals. First, I want to thank my family and my parents in Korea. My wife, Seunghyun Kim, has been very supportive taking care of Ian Jang for her busy husband. I also want to thank my son, Ian Jang, for distracting me when I was under pressure and stress. I would like to thank my parents Seongjae Jang and Kiheung Yoo for their unconditional support. Prof. Flynn has been a very generous and kind advisor. I have lots of respect for him in both technical and personal aspects. I appreciate his support, valuable advices, and jokes. Jaehun Jeong is a great mentor who taught me not only technical material but also how to survive in grad school. I was lucky to work with Rundao Lu, who is an amazingly hard-working guy. Fred N. Buhler is a very nice friend who has helped my writings several times. I also thank Daniel Weyer for his cynical jokes. I thank Seungjong Lee for teaching me analog techniques. I am grateful that I became a friend with Eunseong Moon, the nicest guy in the world. It was great to spend weekends with Junghoon Kim, Minhwa Jang, Wonjin Choi, Hanjin Lim, and their kids. I want to thank Lamsol Woo and Sungwook Yoon for being my best friends from the middle school. Finally, I thank Jeongsong Cultural Foundation for supporting my master’s study, and the Samsung scholarship for supporting my Ph.D. study. ii Table of Contents Acknowledgements ......................................................................................................................... ii List of Tables .................................................................................................................................. v List of Figures ................................................................................................................................ vi List of Abbreviations ...................................................................................................................... x Abstract ......................................................................................................................................... xii Chapter 1 Introduction .................................................................................................................... 1 1.1. Digital Beamforming and 5G ............................................................................................................. 1 1.2. Phased Array and Timed Array ......................................................................................................... 2 ADC Power Comparison for Digital and Analog Beamforming ............................................................. 3 1.3. ............................................................................................................................................................ 3 1.3.1. Thermal Noise Limited ............................................................................................................... 4 1.3.2. Interference Limited.................................................................................................................... 5 1.4. Thesis Outline .................................................................................................................................... 5 Chapter 2 Continuous-Time Band-Pass Delta Sigma Modulator ................................................... 7 2.1. System Architecture ........................................................................................................................... 7 2.2. Advantages of a Continuous Time Modulator over a Discrete-Time Low-Pass Nyquist ADC ........ 8 2.3. Implementation ................................................................................................................................ 10 2.3.1. Digital Array Gain .................................................................................................................... 10 2.3.2. Elimination of the First Return-to-zero DAC ........................................................................... 11 2.3.3. Passive Summer ........................................................................................................................ 12 2.3.4. High Intermediate Frequency (IF) ............................................................................................ 13 2.3.5. 3-stage Nested Gm-C Op-amp .................................................................................................. 14 2.3.6. Constant Output Impedance Feedback DAC ............................................................................ 15 2.4. Comparison with State-of-the-Art ................................................................................................... 16 Chapter 3 Mathematical Analysis ................................................................................................. 17 iii 3.1. Phased Array .................................................................................................................................... 17 3.1.1. Limitations of Phased Arrays .................................................................................................... 19 3.2. RF Timed Arrays ............................................................................................................................. 23 3.2.1. Limitations of RF Timed Arrays ............................................................................................... 24 3.3. Baseband True-Time-Delay ............................................................................................................. 25 3.3.1. The Problem with using Baseband Time Delay Alone ............................................................. 26 3.3.2. Combination of Baseband Time Delay and Phase-Shifting ...................................................... 27 Chapter 4 Implementation............................................................................................................. 29 4.1. Bit Stream Processing (BSP) ........................................................................................................... 29 4.2. Interleaved Bit Stream Processing (IL-BSP) ................................................................................... 32 4.3. True-Time-Delay Digital Beamformer ............................................................................................ 38 Chapter 5 Prototype-I (Phased Array) .......................................................................................... 39 5.1. System Architecture ......................................................................................................................... 39 5.2. Measurements .................................................................................................................................. 40 5.2.1. Wireless Test ............................................................................................................................. 41 5.2.2. Wired Test ................................................................................................................................. 43 5.3. Performance Summary and Comparison ......................................................................................... 49 Chapter 6 Prototype-II (Timed Array) .......................................................................................... 51 6.1. System Architecture ......................................................................................................................... 51 6.2. Measurements .................................................................................................................................. 53 6.2.1. Power Spectral Density Plot and Constellation Diagram ......................................................... 54 6.2.2. Beam Pattern ............................................................................................................................. 55 6.2.3. Interference Test ....................................................................................................................... 57 6.3. Performance Summary and Comparison ......................................................................................... 58 Chapter 7 Future Work ................................................................................................................. 59 Chapter 8 Conclusion .................................................................................................................... 60 Bibliography ................................................................................................................................. 62 iv List of Tables Table I. Prototype-I Phased Array Performance Summary and Comparsion .............................. 49 Table II. Prototype-II Timed Array Performance Summary and Comparsion ............................ 58 v List of Figures Figure 1. System architecture of a conventional phase-shift beamformer and beam squinting errors of a 16-element, 1 GHz IF, a 100 MHz BW beamformer. ............................................................