2009 ISSCC The New Era of Scaling in an SoC World Mark Bohr Intel Senior Fellow Logic Technology Development 1 The End of Scaling is Near? “Optical lithography will reach its limits in the range of 0.75-0.50 microns” “Minimum geometries will saturate in the range of 0.3 to 0.5 microns” “X-ray lithography will be needed below 1 micron” “Minimum gate oxide thickness is limited to ~2 nm” “Copper interconnects will never work” “Scaling will end in ~10 years” Perceived barriers are meant to be surmounted, circumvented or tunneled through 2 Outline • Transistor Scaling • Microprocessor Evolution • Vision of the Future 3 Scaling Trends 10 CPU Transistor Count 10 9 2x every 2 years 1 10 7 Microns 0.1 10 5 3 0.01 10 1970 1980 1990 2000 2010 2020 Transistor dimensions scale to improve performance, reduce power and reduce cost per transistor 4 Scaling Trends 10 CPU Transistor Count 10 9 2x every 2 years 1 10 7 Microns 0.1 65nm 10 5 45nm Feature Size 32nm 0.7x every 2 years 3 0.01 10 1970 1980 1990 2000 2010 2020 Transistor dimensions scale to improve performance, reduce power and reduce cost per transistor 5 MOSFET Scaling Device or Circuit Parameter Scaling Factor Device dimension tox, L, W 1/ κ Doping concentration Na κ Voltage V 1/ κ Current I 1/ κ Capacitance εA/t 1/ κ Delay time/circuit VC/I 1/ κ Power dissipation/circuit VI 1/ κ2 Power density VI/A 1 R. Dennard, IEEE JSSC, 1974 Classical MOSFET scaling was first described in 1974 6 30 Years of MOSFET Scaling Dennard 1974 Intel 2005 1 µm Gate Length: 1.0 µm 35 nm Gate Oxide Thickness: 35 nm 1.2 nm Operating Voltage: 4.0 V 1.2 V Classical scaling ended in the early 2000s due to gate oxide leakage limits 7 90 nm Strained Silicon Transistors NMOS PMOS High Stress Film SiGe SiGe SiN cap layer SiGe source-drain Tensile channel strain Compressive channel strain Strained silicon provided increased drive currents, making up for lack of gate oxide scaling 8 High-k + Metal Gate Transistors 65 nm Transistor 45 nm HK+MG SiO 2 dielectric Hafnium-based dielectric Polysilicon gate electrode Metal gate electrode High-k + metal gate transistors break through gate oxide scaling barrier 9 Transistor Performance Increase NMOS PMOS 1000 1000 1.0 V 1.0 V 65nm 45nm 65nm 45nm 100 +12% 100 +50% (nA/um) 5x (nA/um) 100x OFF OFF I 10 I 10 1 1 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ION (mA/um) ION (mA/um) 45 nm HK+MG provides average 30% drive current increase or >5x I OFF leakage reduction Ref. K. Mistry, IEDM ’07 10 Gate Leakage Reduction 100 SiON/Poly 65nm 10 25x 1 SiON/Poly 65nm 0.1 1000x 0.01 0.001 HiK+MG 45nm HiK+MG 45nm 0.0001 Normalized Gate Leakage PMOS NMOS 0.00001 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 VGS (V) HK+MG significantly reduces gate leakage 11 Bitcell Leakage Reduction 12 1.0V 25C 10 8 6 IGATE 10x 4 IOFF 2 Normalized Cell Leakage Cell Normalized IJUNCT 0 65nm 45nm SRAM bitcell leakage reduced ~10x 12 VT Variability Reduction 1.1 1 Minimal oxide scale HiK+MG 0.9 C2 0.8 Less V T Normalized 0.7 variation to 180nm Tox scaling 0.6 0.5 0.4 180nm 130nm 90nm 65nm 45nm 4 4q3ε φ T 4 N 1 Cc σV = si B ⋅ ox ⋅ = 22 ( Tran 2 εox Leff ⋅ Zeff 2 Leff ⋅ Zeff HK+MG provides oxide scaling needed for variability reduction Ref. K. Kuhn, IEDM ’07 13 Interconnect Trends 10 10 8 6 M2 Pitch # Metal 1 (um) Layers 4 0.7x per 2 generation 0.1 0 500 350 250 180 130 90 65 45 32 Technology Generation (nm) Added metal layers + material improvements enable interconnect scaling 14 Interconnect Trends 10 10 8 6 M2 Pitch # Metal 1 (um) Layers 4 0.7x per 2 generation 0.1 0 500 350 250 180 130 90 65 45 32 Technology Generation (nm) Added metal layers + material improvements enable interconnect scaling 15 Interconnect Trends 10 10 8 6 M2 Pitch # Metal 1 (um) Layers 4 SiO 2 SiOF Low-k Lower-k 2 Al Cu 0.1 0 500 350 250 180 130 90 65 45 32 Technology Generation (nm) Added metal layers + material improvements enable interconnect scaling 16 45 nm Interconnects Pitch (nm) M8 810 Loose pitch + thick metal on upper layers M7 560 Cu • High speed global wires Low-k • Low resistance power grid M6 360 M5 280 Tight pitch on lower layers M4 240 • Maximum density for M3 160 local interconnects M2 160 M1 160 Hierarchical interconnect pitches 17 45 nm Interconnects Polymer M9 7 µm Cu M1-8 Thick M9 for very low resistance on-die power routing 18 45 nm Microprocessor Products Quad Core Dual Core Single Core 6 Core 8 Core 45 nm process serves microprocessor applications from low power to high performance 19 32 nm Generation 10 1 Microns 0.1 32nm 0.01 1970 1980 1990 2000 2010 2020 20 32 nm Logic Technology • 2nd generation high-k + metal gate transistors - High-k EOT scaled from 1.0 nm to 0.9 nm - Replacement metal gate process flow - 4th generation strained silicon • 9 copper + low-k interconnect layers - Hierarchical interconnect pitches - Thick M9 for power routing • Immersion lithography on critical layers - 70% transistor and interconnect pitch scaling - 50% SRAM cell area scaling • Pb-free and halogen-free packages Higher performance, lower power, lower cost per transistor 21 Contacted Gate Pitch Trend 1000 Pitch Gate Pitch (nm) 0.7x every 2 years 32 nm Generation 100 112.5 nm Pitch 1995 2000 2005 2010 Transistor gate pitch continues to scale 0.7x every 2 years 22 Transistor Performance 2.0 2.0 1.0 V, 100 nA I OFF 32nm 1.5 45nm 1.5 65nm Drive 90nm Current 1.0 1.0 (mA/um) 130nm NMOS 0.5 0.5 PMOS 0.0 0.0 1000 100 Gate Pitch (nm) Drive currents continue to increase while gate pitch scales 23 32 nm Interconnects 8 um Cu M9 Pitch (nm) M8 566.5 M7 450.1 M6 337.6 M5 225.0 M4 168.8 M3 112.5 M2 112.5 M1 112.5 Hierarchical interconnect pitches 24 SRAM Cell Size Scaling 10 Cell Area 1 (um 2) 0.5x every 2 years 32 nm Generation 0.171 um 2 Cell 0.1 1995 2000 2005 2010 Transistor density continues to double every 2 years 25 SRAM Cell Scaling 65 nm 0.570 µm2 45 nm 0.346 µm2 32 nm 0.171 µm2 Good pattern resolution while scaling feature size and continuing with 193 nm exposure wavelength 26 32 nm SRAM Test Chip • 291 Mbit • 0.171 um 2 cell size • >1.9 billion transistors • >3.8 GHz operation • Functional silicon in Aug ‘07 32 nm SRAM test vehicle included all transistor and interconnect features used on 32 nm microprocessors Ref. Y. Wang, paper 27.1, ISSCC ’09 27 30 Years of Scaling Contact 1978 Ten 32nm SRAM Cells 2008 1 µm 28 The Old Era of Device Scaling Device or Circuit Parameter Scaling Factor Device dimension tox, L, W 1/ κ Doping concentration Na κ Voltage V 1/ κ Current I 1/ κ Capacitance εA/t 1/ κ Delay time/circuit VC/I 1/ κ Power dissipation/circuit VI 1/ κ2 Power density VI/A 1 It has served us well for >30 years 29 The New Era of Device Scaling SiGe SiGe Copper + Low-k Strained Silicon High-k + Metal Gate Modern CMOS scaling is as much about material and structure innovation as dimensional scaling 30 Outline • Transistor Scaling • Microprocessor Evolution • Vision of the Future 31 Microprocessor Evolution More transistors Higher frequency More data bits per cycle Instruction parallelism Out-of-order issue Multi-threading Many of these innovations have been for improved performance, now the challenge is to innovate for power efficiency 32 45 nm Nehalem CPU Modern microprocessors are a complex system on a chip with multiple functional units and multiple interfaces 33 45 nm Nehalem CPU 23 master DLL circuits 11 PLL circuits 5 digital thermal sensors Multiple clocking domains, local control 34 SRAM Dynamic Sleep Transistors Normal SRAM Sleep transistors V DD sub-block leakage shut off leakage in inactive sub-blocks SRAM Cache Sub-Block Sleep Sleep Control Transistor IREM images showing banks being accessed VSS 5-10x leakage reduction during “retention/standby” Ref. K. Zhang, VLSI Circuits ‘04 35 Integrated Power Gates Thick On-Die (M9) VCC Interconnect Layer Power Gates Core0 Core1 Core2 Core3 Nehalem Memory System, Cache, I/O VTT • Shuts off both switching power and leakage power • Enables idle cores to go to ~0 power, independent of state of other cores on die Ref. R. Kumar, paper 3.2, ISSCC ’09 36 Power Gates Enabled with Design+Process Co-optimization M9 M1-8 Thick metal 9 layer for low Ultra-low leakage transistor for resistance on-die power routing high off-resistance power gates 37 Dynamically delivering optimal performance and ener and performance optimal delivering Dynamically Frequency Many threaded workloads threaded Lightly workloads - • All cores operating Core 0 Core 1 Core 2 Nehalem Mode Turbo Core 3 • Higher frequency for active cores • power Zero for inactive cores • Power gates shut off some cores Core 0 Core 1 Core 2 Core 3 Ref.