Historical Perspective Ramon Canal CTD – Master CANS 1 Agenda • Back in the old days • Back to the future 2 The First Computer The Babbage Difference Engine (1832) 25,000 parts cost: £17,470 3 ENIAC - The first electronic computer (1946) 4 The Transistor Revolution First transistor Bell Labs, 1948 5 The First Integrated Circuits Bipolar logic 1960’s ECL 3-input Gate Motorola 1966 6 Intel 4004 Micro-Processor 1971 1000 NMOS transistors 1 MHz operation 7 Intel Westmere microprocessor (6C) 2010 1’17B CMOS transistors ~3 GHz operation 32nm 8 AMD “Istanbul” microprocessor 2009/2010 900+ M CMOS transistors ~3 GHz operation 45nm 9 Agenda • Back in the old days • Back to the future 10 Electronics LOG2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION 10 11 12 13 14 15 16 , April 19, 1965. 0 1 2 3 4 5 6 7 8 9 1959 Moore s 1960 1961 1962 1963 1964 1965 1966 ’ s Law 1967 1968 Law 1969 1970 1971 1972 1973 1974 1975 11 Transistor number 1 Billion K Transistors 1,000,000 Conroe 100,000 Pentium IV Pentium® III 10,000 Pentium® II Pentium® Pro 1,000 Pentium® i486 100 i386 80286 10 8086 1 1975 1980 1985 1990 1995 2000 2005 2010 PditiPrediction 12 Clock rate 1. ? every 2 years 10000 DblDoubles every 1000 Conroe 2 years Netburst Mhz) 100 P6 Pentium ® proc 486 uency ( 10 386 qq 8085 8086 286 Fre 1 8080 8008 4004 0.1 1970 1980 1990 2000 2010 Year 13 Power Density 1000 Rocket Nozzle Nuclear reactor 2 100 Pentium® 4 /cm ss Hot plate Pentium® III Pentium® II Watt 10 Pentium® Pro i386 Pentium® i486 1 “New Microarchitecture Challenges in the CoComingming Generations of CMOS Process Technologies ” – PowerFred Pollack, density Intel Corp. is Micro32 too conferencehigh to key keep note - the 1999. contacts cool enough Puerto Rico, March 2006 14 Power dissipation ... for cooking ? 15 16 17 Productivity Trends 10,000 100,000 10,000,000(M) 100,000,000 pp Tr. Logic/Chip 1,000,0001,000 10,000,00010,000 Tr./Eng. Mes 100,000100 1,000,0001,000 -Mes at itat ic per Chi tt xx 10 58%/Any 100 10,000 Creixement Complexitat 100,000 1,0001 10,00010 Comple roductivi rans./Eng istors Log PP x TT 0.1 x 1 100 x x 1,000 x 21%/Any x x (K) x Creixement Productivitat Trans 0.0110 1000.1 0. 0011 100010.01 2003 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2005 2007 2009 SSthSource: Sematech Complexity grows faster than design productivity Courtesy, ITRS Roadmap 18 Technology Scaling • Technology shrinks 0. 7x per generation • Each new generation can integrate 2x more functions per chip; the cost per chip is not affected significantly • Thus... Th e cost per f uncti on d ecreases two f old • But... – How can we design a chip with more functions? – Engineering population doesn‘t double every 2 years • So: we need better and efficient design techniques: – Take advantage of abstraction levels 19 Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT DEVICE G S D n+ n+ 20 Cost per Transistor cost: ¢-per-transistor 1 0.1 Cost of fabrication per transistor (Moore’s Law) 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012 21 Some examples (1994) Xip Metal Line Wafer Defects Area Dies/ Yield Die 2 Layers width Cost / cm mm2 wafer cost 386DX 2 0.90 $900 1.0 43 360 71% $4 486 DX2 3 0800.80 $1200 101.0 81 181 54% $12 Power PC 4 0.80 $1700 1.3 121 115 28% $53 601 HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73 DEC Alpha 3 0700.70 $1500 121.2 234 53 19% $149 Super 3 0.70 $1700 1.6 256 48 13% $272 Sparc Pentium 3 0.80 $1500 1.5 296 40 9% $417 22 Design tools • VLSI system design is a complex process which requires automatization of the synthesis cycle. That’s why we need design tools. • There are three families of tools: – Synthesis tools • They allow a physical representation of circuits expressde in HDL (Hardware Definition Languages). – Analysis and Verification • They guarantee the specifications and the correctness of the design – Testing tools • They verify that there have been no errors on the fabrication process. 23 Historical Perspective Ramon Canal CTD – Master CANS CTD – Master CANS 24.