NANOELECTRONICS: TECHNOLOGY ASSESSMENT AND PROJECTION AT THE DEVICE, CIRCUIT, AND SYSTEM LEVEL A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHYLOSOPHY Lan Wei August 2010 © 2010 by Lan Wei. All Rights Reserved. Re-distributed by Stanford University under license with the author. This work is licensed under a Creative Commons Attribution- Noncommercial 3.0 United States License. http://creativecommons.org/licenses/by-nc/3.0/us/ This dissertation is online at: http://purl.stanford.edu/mj834nb2809 ii I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Philip Wong, Primary Adviser I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Subhasish Mitra I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Krishna Saraswat Approved for the Stanford University Committee on Graduate Studies. Patricia J. Gumport, Vice Provost Graduate Education This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file in University Archives. iii iv ABSTRACT In the past thirty years, semiconductor industry has been making steady progress to improve the intrinsic Si-based device performance while reducing the device size simply by scaling down the devices in all three dimensions, as proposed by R. Dennard in the 1970s. However, the improvement of intrinsic device performance based on Dennard scaling is approaching its limit with non-scalable supply voltage, leakage currents and non-negligible parasitic capacitances and resistances. Continued progress in nanoelectronics necessitates a holistic view that crosses the traditional boundaries of device, circuit, and system. The best devices are those that are optimized for the circuits and systems of the target application. Device design and engineering must aim at improvement at the circuit and system level. In this thesis, the design space is explored for future Si CMOS technology, and carbon nanotube field effect transistor, a promising technology in the post-Si era. Compact models of transport properties and capacitive components of different device structures have been developed to facilitate circuit-level analysis and system-level optimization. Possible ways of extending technology roadmap are proposed. When Dennard scaling is becoming less effective, technology boosters are introduced to improve the device intrinsic performance. Currently, the main approaches are enhancing the device intrinsic transport property (e.g. introducing strain and novel channel materials) and strengthening the device intrinsic electrostatic integrity (e.g. SOI, FinFET, high-k/metal gate). The conventional ways of technology assessment focus on the intrinsic device-level characteristics under certain bias conditions, regardless of the details of the operating conditions. Our study shows the importance of comprehending the circuit environment and system application when benchmarking v device performance. As a general guideline for future technology development, enhancing the transport property is a key booster for circuits with un-stacked logic gates and high-performance applications, while strengthening the electrostatic integrity is preferred for circuits with stacked logic gates and low-power applications. As the non-scalable parasitic capacitances and resistances are no longer negligible comparing to the intrinsic properties, the device-level parasitic components become critical for circuit-level performance. Parasitic engineering is inevitable for future technology generations. We analyze the geometric and electrical properties of different capacitance components and develop compact models for a variety of conventional and emerging device structures, including bulk devices, fully-depleted silicon-on-insulator (FDSOI) devices, planar double gate (DG) devices, and one- dimensional nanowire/nanotube devices. With the models, we carefully examine the impact of different device parasitic capacitances on circuit- performance. When the physical gate length can no longer be effectively scaled down and traditional boosters (e.g., strain, high-k/metal gate) are having diminishing return, engineering the parasitic components by “selective device structure scaling” becomes the most fruitful path to extend the technology roadmap. By judiciously engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, selective device structure scaling will enable technology scaling and contacted gate pitch scaling for several generations beyond the currently perceived limits. For a fully custom designed 53-bit multiplier, the selectively scaled devices with reduced footprint achieve 30% smaller layout area, 25% higher speed and 10% energy efficiency, compared with conventional devices. Beyond Si CMOS scaling, carbon nanotube field effect transistor (CNFET) is among the promising candidates to extend the technology. Device level analyses have suggested significant benefits, but it is not clear what the circuit/system benefits are, at the chip-level. We take an application-oriented approach, as opposed to the device- level modeling employed in previous works. A fast, non-iterative analytical model for vi CNFET has been developed, including both carrier transport and capacitance components which are the key determinants of performance. The chip-level system (processor plus on-chip cache) performance of CNFET technology has been optimized and compared with Si-based technology. The optimization results show that CNFET chip can operate as 5 times faster than partially-depleted silicon-on-insulator (PDSOI) chip, at the same chip power level from 0.01W to 100W. The optimization methodology and platform can be potentially transplanted to other emerging devices. Besides full chip-level optimization, simple technology assessment and optimization methodologies are also required, especially at the early development stage of a new technology. Conventionally, aspiring emerging device technologies (e.g. III-V, CNFET, TFET) are often targeted to outperform Si FETs at the same off-state current (Ioff) and supply voltage (Vdd). We present a new device technology assessment methodology based on energy-delay optimization which treats Ioff and Vdd as “free variables”, and bounded by constraints due to device variation and circuit noise margin. We show that for each emerging device (III-V, CNFET, TFET), there is a corresponding and different optimal set of Ioff and Vdd, and an optimal energy-delay. Today’s best-available III-V and CNFET can outperform the best Si FET by 1.5-2x and 2-3.5x, respectively. Projected into the 10nm gate length regime, III-V-on- Insulator, CNFET, and TFET are 1.25x, 2-3x, and 5-10x (for FO1 delays of 0.3ns, 0.1ns, and 1ns respectively) better than the ITRS target at the same gate length. In conclusion, this thesis addresses the significance of a holistic view across the traditional boundaries of device, circuit, and system in technology assessment and projection. Guided by this concept, we chart a new path for Si CMOS technology scaling for future technology generations. We also accomplish for the first time chip- level performance assessment and optimization of new emerging transistors such as CNFETs. This establishes a new benchmark and design methodology for emerging nanoelectronics. vii viii ACKNOWLEDGMENTS I wish to acknowledge the people who have made my 5-year experience at Stanford a very pleasant and fruitful journey. This dissertation would not have been possible without the supervision and support from my Principle Advisor, Prof. H. –S. Philip Wong. As a distinguished researcher, he has provided excellent technical guidance in every stage of my Ph. D. research through his vast knowledge and experience. As an outstanding mentor, Prof. Wong always respects his students and takes into consideration their long-term growth as a priority. I owe him my deepest gratitude for his support and encouragement for a lot of my achievements here at Stanford. I would also like to thank Prof. Krishna Saraswat, Prof. Subhasish Mitra, and Prof. Ada Poon. Through his technical insights, Prof. Saraswat has given me invaluable suggestions in regards to both my research and career development. I am fortunate to have been a part of the “carbon nanotube club” led by Prof. Mitra and Prof. Wong. As a successful and energetic junior faculty, Prof. Mitra is the key person to keep the club active, supportive, and productive. Prof. Ada Poon is not only the person who guided me into the bioengineering area, but also a trustable and caring friend who has given me precious advice on both work and life. I am heartily thankful to my industrial mentors and other academic advisors. In particular, I have greatly benefited from Dr. David J. Frank at IBM Research and Dr. Frédéric Boeuf at STMicroelectronics, with whom I have intensively collaborated. Discussions with them are always inspiring, and they never hesitate to offer their help or share their thoughts, knowledge, and experience.