Sådhanå (2018) 43:94 Ó Indian Academy of Sciences https://doi.org/10.1007/s12046-018-0913-z Sadhana(0123456789().,-volV)FT3](0123456789().,-volV) A fully integrated high IP1dB CMOS SPDT switch using stacked transistors for 2.4 GHz TDD transceiver applications PAUL SCHMIEDEKE1,2, MOHAMMAD ARIF SOBHAN BHUIYAN2,5,*, MAMUN BIN IBNE REAZ2, TAE GYU CHANG3, MARIA LIZ CRESPO4 and ANDRES CICUTTIN4 1 Fakulta¨tfu¨r Elektrotechnik, Informationstechnik, Physik, Technische Universita¨t Braunschweig, Hans- Sommer-Str. 66, 38106 Brunswick, Germany 2 Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia 3 School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 156-756, Korea 4 The Abdus Salam International Centre for Theoretical Physics, Via Beirut 31, 34100 Trieste, Italy 5 Department of Electrical and Electronics Engineering, Xiamen University Malaysia, Jalan Sunsuria, Bandar Sunsuria, 43900 Sepang, Selangor, Malaysia e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected] MS received 18 February 2016; revised 5 September 2017; accepted 13 September 2017; published online 7 June 2018 Abstract. A transmit/receive (T/R) switch is an essential module of every modern time division duplex (TDD) transceiver circuit. A T/R switch with high power handling capacity in CMOS process is difficult to design due to capacitive coupling of radio frequency signals to the substrate. This paper proposes a single-pole-double- throw (SPDT) T/R switch designed in a standard Silterra 130 nm CMOS process for high-power applications like RFID readers. The results reveal that, in 2.4 GHz ISM band, the proposed switch exhibits a very high input P1dB of 39 dBm with insertion loss of only 0.34 dB and isolation of 40 dB in transmit mode but 1.08 dB insertion loss and 30 dB isolation in receive mode. Stacked thick-oxide triple-well transistors, resistive body floating and negative control voltages are used to achieve such lucrative performance. Moreover, the chip size of the designed switch is only 0.034 mm2 as bulky inductors and capacitors are avoided. The Monte-Carlo and corner analyses confirm that the performance of the switch is also quite stable and reliable. Keywords. CMOS; ISM band; SPDT; T/R switch; transceiver. 1. Introduction In a time division duplex (TDD) system, the same antenna is used for the reception as well as for the trans- Radio frequency (RF) switch is an essential module in RF mission of signal to improve system portability and reduce communications systems. In RF transceivers, it is used to cost as shown in figure 1. Therefore, in every TDD trans- switch among different circuits and/or modules as well as to ceiver, a transmit/receive (T/R) switch is necessary for its share them to make the design compact and cost-efficient. proper functioning. The switch performance is crucial for Because of the widespread mobile communication systems, the performance of the entire system, because it is the first much attention in RF transceiver research has been focus- as well as the last stage of the transceiver and directly sed on high-performance integrated designs. Moreover, the affects the quality of the transmitted or received signal [5]. continuous advancement of CMOS process makes it the In CMOS T/R switch fabrication, the critical design most promising technology for realizing RF transceivers considerations include mainly low insertion loss (IL), high [1, 2]. As a result, RF switches used in RF communication isolation and high power-handling capability (P1dB). circuits have evolved from implementations of PIN diode, However, these performances commonly are trade-offs PHEMTs, MESFETs, GaAs components, etc. to ones using with each other. Therefore, designing T/R switches with CMOS because of problems like high power consumption, adequate performance becomes more challenging in bulk large size and long-term reliability [3, 4]. CMOS technology. To meet the performance requirements of T/R switches in standard CMOS technology, extensive research is going on all over the world [6]. Yamamoto et al *For correspondence 1 94 Page 2 of 7 Sådhanå (2018) 43:94 used simultaneously to obtain high-performance series- shunt T/R switch in 2.4 GHz ISM band from 130 nm CMOS technology. At the same time, avoiding the usage of bulky inductors and capacitors in the circuit resulted in achieving very small chip size. Such a switch will be very useful for 2.4 GHz ISM band RF transceivers. 2. Proposed T/R switch design Figure 1. T/R switch in a typical TDD transceiver front-end. Figure 2 shows the basic design of a series-shunt T/R switch. In the transmit mode, the series transistor M1 pro- (2001) illustrated the basic concerns for better performance vides a low impedance path (M1 is ON) between the of a classic series-shunt type T/R switch by implementing antenna (ANT) and the transmitter (TX) whereas M2 gate width optimization of the MOSs. Although the design remains turned off and therefore isolates the receiver (RX) exhibited low isolation and low power handling capacity, as from the antenna (ANT). The shunt transistors at the TX a result of using large CMOSs, the area of the total chip was (M3) and RX (M4) node improve the isolation of the switch large [7]. For further improvement in performance, Feng by providing a low impedance path for the leakage signal and Karmin (2001) introduced DC biasing of transistors from the unneeded signal node (in transmit mode therefore along with their proper optimization in the gate. This from RX) to ground. In the transmit mode, M3 is switched resulted in low IL along with moderate isolation and power off and M4 is on. In the receive mode, all on- and off-states handling capacity. However, relatively higher control of transistors are reversed. The gate resistors allow the gate voltages (6.0/2.0 V) were used and the area of the layout node of the transistors to float at the operating frequency. was also reduced to a half, which is still large compared This helps minimize the voltage fluctuations at the gate with concurrent CMOS switch circuits [8]. terminal and keeps the switching speed stable [17]. Feng and Kenneth (2004) and Hove et al (2004) The on-state resistance of a MOS is given by the fol- improved the isolation and IL of the switch by utilizing lowing well-known equation: impedance transformation and parasitic MOSFET model, respectively [9, 10]. However, power handling capacity of 1 Ron ¼ W ð1Þ both the circuits was not adequate and the layout areas of lnCox L ðVGS À VTHÞ the switches were also large. In the same year Talwalkar et al (2004) adopted increased substrate impedance tech- where ln is the mobility of electrons and Cox represents nique to offer a narrowband resonance, but with an capacitance per unit area of the gate. increased chip area due to additional on-chip inductors In order to achieve low IL, the on-state resistance of the [11]. Bhatti et al (2005) introduced a transformer-based transistors is needed to be lowered. As the electron mobility T/R switch only for low-power applications but with many of the NMOSs is higher, n-channel transistors have been complex matching requirements [12]. Mei et al (2006) preferred for this design. The performance of the switch utilized resistive body floating technique to improve the overall performance of the switch, but the power handling capacity and isolation of the switch were not adequate for high-power transceivers. Nevertheless, they reduced the size of the chip [13]. Mekanand et al (2008) designed a switch by paralleling an NMOS and a PMOS instead of a single MOS to improve the dynamic range in the con- ducting state, but the IL of the switch was more than 1 dB [14]. Dinc et al (2012) used inductors in parallel to switching transistors in order to form a parallel tank circuit and cancel out some of the transistors’ off-state drain– source capacitance [15]. This helped improve the isolation of the switch but in effect it left very high die area because of bulky on-chip inductor. Liu et al (2012) implemented the higher saturation voltage property of asymmetric transistors to improve the IL and power handling capacity but the chip area of the switch was still quite high [16]. In this paper, stacked thick-oxide triple-well transistors, resistive body floating and negative control voltages are Figure 2. A typical series-shunt T/R switch circuit. Sådhanå (2018) 43:94 Page 3 of 7 94 Figure 3. Schematic circuit of the proposed T/R switch. with large input power can be improved if the gate control One accountable problem of such a switch is the off-state voltage of the transistors is increased. Besides, to manage current flowing through the shunt transistor, which increa- the high gate to channel voltage, thick oxide transistors are ses largely if the drain–source voltage of the transistor gets used in this switch. Triple-well transistor structure is too high [19]. Since the peak voltage of a 40 dBm signal to implemented to realize a better isolation from the silicon ground in a 50 X environment is equal to more than 30 V, substrate to minimize losses at high frequencies due to its it is useful to stack multiple transistors in series to reduce low resistance and the parasitic capacitances connecting it the drain–source voltage of a single transistor [20]. with the channel [18]. Therefore the transistors M2 and M3 of (figure 2) have to The optimizations of the number of transistors and their be replaced by multiple transistors in series, because these aspect ratios are very important when designing a switch transistors need to be able to block the high power signal to with a certain design goal.