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'37+4'& Preliminary Revision 0.1, October 9, 2000 -i- Revision History 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A TABLE OF CONTENTS REVISION HISTORY........................................................................................................................................................................I TABLE OF CONTENTS.................................................................................................................................................................. II LIST OF FIGURES..........................................................................................................................................................................III LIST OF TABLES ...........................................................................................................................................................................IV KT133A AMD ATHLON™ NORTH BRIDGE .............................................................................................................................. 1 OVERVIEW ....................................................................................................................................................................................... 4 PINOUTS .......................................................................................................................................................................................... 6 PIN DESCRIPTIONS ........................................................................................................................................................................ 9 REGISTERS..................................................................................................................................................................................... 17 REGISTER OVERVIEW ................................................................................................................................................................. 17 MISCELLANEOUS I/O................................................................................................................................................................... 21 CONFIGURATION SPACE I/O ....................................................................................................................................................... 21 REGISTER DESCRIPTIONS............................................................................................................................................................ 22 Device 0 Header Registers - Host Bridge............................................................................................................................ 22 Device 0 Configuration Registers - Host Bridge ................................................................................................................ 24 Host CPU Control................................................................................................................................................................................. 24 DRAM Control ..................................................................................................................................................................................... 25 PCI Bus Control.................................................................................................................................................................................... 30 GART / Graphics Aperture Control ...................................................................................................................................................... 34 AGP Control ......................................................................................................................................................................................... 36 Device 1 Header Registers - PCI-to-PCI Bridge ................................................................................................................ 41 Device 1 Configuration Registers - PCI-to-PCI Bridge..................................................................................................... 43 AGP Bus Control .................................................................................................................................................................................. 43 ELECTRICAL SPECIFICATIONS............................................................................................................................................... 46 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................... .................. 46 DC CHARACTERISTICS................................................................................................................................................................ 46 POWER CHARACTERISTICS ......................................................................................................................................................... 47 AC TIMING SPECIFICATIONS ...................................................................................................................................................... 47 MECHANICAL 10(+&'06+#.SPECIFICATIONS............................................................................................................................................. 48 '37+4'& Preliminary Revision 0.1, October 9, 2000 -ii- Table of Contents 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133A - VT8363A LIST OF FIGURES FIGURE 1. KT133A SYSTEM BLOCK DIAGRAM USING THE VT82C686A SOUTH BRIDGE........................................ 4 FIGURE 2. VT8363A KT133A BALL DIAGRAM (TOP VIEW)................................................................................................ 6 FIGURE 3. CPU / SDRAM / AGP / PCI CLOCK CONNECTIONS ......................................................................................... 15 FIGURE 4. GRAPHICS APERTURE ADDRESS TRANSLATION ........................................................................................