Instruction Set Architecture ISA = Programmer-visible components & operations • Memory organization Address space -- how may locations can be addressed? Addressibility -- how many bits per location? • Register set Chapter 5 How many? What size? How are they used? • Instruction set The LC-3 Opcodes Data types Addressing modes All information needed to write/gen machine language program Based on slides © McGraw-Hill Additional material © 2004/2005 Lewis/Martin CSE 240 5-2 LC-3 Overview: Memory and Registers LC-3 Overview: Instruction Set Memory Opcodes • Address space: 216 locations (16-bit addresses) • 16 opcodes • Addressibility: 16 bits • Operate instructions: ADD, AND, NOT, (MUL) • Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI Registers • Control instructions: BR, JSR, JSRR, RET, RTI, TRAP • Temporary storage, accessed in a single machine cycle • Some opcodes set/clear condition codes, based on result Memory access generally takes longer N = negative (<0), Z = zero (=0), P = positive (> 0) • Eight general-purpose registers: R0 - R7 Data Types Each 16 bits wide • 16-bit 2’s complement integer How many bits to uniquely identify a register? Addressing Modes • Other registers • How is the location of an operand specified? Not directly addressable, but used by (and affected by) • Non-memory addresses: register, immediate (literal) instructions PC (program counter), condition codes, MAR, MDR, etc. • Memory addresses: base+offset, PC-relative, indirect CSE 240 5-3 CSE 240 5-4 1 LC-3 Instruction Summary Operate Instructions (inside back cover) Only three operations • ADD, AND, NOT Source and destination operands are registers • Do not reference memory • ADD and AND can use “immediate” mode, (i.e., one operand is hard-wired into instruction) Will show abstracted datapath with each instruction • Illustrate when and where data moves to accomplish desired op. CSE 240 5-5 CSE 240 5-6 NOT (Register) ADD (Register) this zero means “register mode” 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT 1 0 0 1 DR SR 1 1 1 1 1 1 ADD 0 0 0 1 DR SR1 0 0 0 SR2 Register File Register File ADD R3 R5 R0 ADD R3 R5 R0 R0 1111111111111111 IR 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 IR 0 0 0 1 0 1 1 1 0 1 0 0 0 0 0 0 R1 R1 R2 R2 R3 0101000011110000 R3 0000000000001000 R4 R4 Convention R5 1010111100001111 R5 0000000000001001 R6 16 R6 16 source R7 R7 destination 16 16 16 16 B A B A NOT ADD ALU ALU Note: DR and SR could be the same register CSE 240 5-7 CSE 240 5-8 2 ADD (Immediate) this one means “immediate mode” Using Operate Instructions: Subtraction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 How do we subtract two numbers? ADD 0 0 0 1 DR SR1 1 imm5 Goal Register File ADD R3 R5 -1 R0 • R1 <- R2 - R3 (no such instruction!) IR 0 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 R1 5 R2 R3 0000000000001000 Idea (Use 2’s complement) SEXT R4 16 R5 0000000000001001 1. R1 <- NOT R3 R6 16 1111111111111111 R7 2. R1 <- R1 + 1 16 16 3. R1 <- R2 + R1 1 0 16 B A ADD ALU If 2nd operand is known and small, easy • R1 <- R2 + -3 CSE 240 5-9 CSE 240 5-10 Using Operate Instructions: OR Using Operate Instructions: Copying How do we OR two numbers? How do we copy a number from register to register? Goal Goal • R1 <- R2 OR R3 (no such instruction!) • R1 <- R2 (no such instruction!) Idea (Use DeMorgan’s Law) Idea (Use immediate) • A OR B = NOT(NOT(A) AND NOT(B)) • R1 <- R2 + 0 1. R4 <- NOT R2 2. R5 <- NOT R3 Could we use AND? 3. R1 <- R4 AND R5 4. R5 <- NOT R1 CSE 240 5-11 CSE 240 5-12 3 Using Operate Instructions: Clearing Data Movement Instructions How do we set a register to 0? Load: read data from memory to register • LD: PC-relative mode Goal • LDR: base+offset mode • LDI: indirect mode • R1 <- 0 (no such instruction!) Idea Store: write data from register to memory • R1 <- R1 AND 0 • ST: PC-relative mode • STR: base+offset mode • STI: indirect mode Could we use ADD? Load effective address • Compute address, save in register, do not access memory • LEA: immediate mode CSE 240 5-13 CSE 240 5-14 PC-Relative Addressing Mode LD (PC-Relative) Want to specify address directly in the instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 • But an address is 16 bits, and so is an instruction! LD 0 0 1 0 DR PCoffset9 • After subtracting 4 bits for opcode and 3 bits for register, we have 9 bits available for address Register File LD R3 -81 R0 IR 0 0 0 1 0 1 1 1 1 0 1 0 1 1 1 1 R1 Observation 9 R2 • Needed data often near currently executing instruction R3 0000000000001001 PC 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 SEXT R4 16 R5 16 16 R6 Solution 1111111110101111 R7 • Add 9 bits in instruction (sign extended) to PC (of next instruction) to form address B A ADD ALU MAR MEMORY MDR Example: LD: R1 <- M[PC+SEXT(IR[8:0])] 16 Rd CSE 240 5-15 CSE 240 5-16 4 ST (PC-Relative) Base + Offset Addressing Mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Problem ST 0 0 1 1 SR PCoffset9 • With PC-relative mode, can only address words “near” the instruction • What about the rest of memory? Register File ST R3 -81 R0 IR 0 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 R1 Solution 9 R2 • Use a register to generate a full 16-bit address R3 0000000000001001 PC 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 SEXT R4 16 R5 16 Idea R6 16 1111111110101111 R7 • 4 bits for opcode, 3 for src/dest register, 3 bits for base register • Remaining 6 bits are used as a signed offset B A • Offset is sign-extended before adding to base register ADD ALU • I.e., Instead of adding offset to PC, add it to base register MAR MEMORY MDR 16 Wr Example: LDR: R1 <- M[R2+SEXT(IR[5:0])] CSE 240 5-17 CSE 240 5-18 LDR (Base+Offset) STR (Base+Offset) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LDR 0 1 1 0 DR BaseR offset6 STR 0 1 1 1 SR BaseR offset6 Register File Register File LDR R3 R5 -17 R0 STR R3 R5 -17 R0 IR 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 1 IR 0 1 1 1 0 1 1 1 0 1 1 0 1 1 1 1 R1 R1 6 R2 6 R2 R3 0000000000001001 R3 0000000000001001 SEXT R4 SEXT R4 16 R5 000000001000000 16 R5 000000001000000 R6 16 R6 16 1111111111101111 R7 1111111111101111 R7 16 16 B A B A ADD ADD ALU ALU MAR MEMORY MDR MAR MEMORY MDR 16 16 Rd Wr CSE 240 5-19 CSE 240 5-20 5 Indirect Addressing Mode LDI (Indirect) Another way to produce full 16-bit address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 • Read address from memory location, then load/store to that address LDI 1 0 1 0 DR PCoffset9 Steps Register File • Address is generated from PC and PCoffset (just like PC-relative LDI R3 -17 R0 IR 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 addressing) R1 9 • Then content of that address is used as address for load/store R2 R3 0000000000001001 PC 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 SEXT R4 16 16 R5 Example: LDI: R1 <- M[M[PC+SEXT(IR([8:0])] 16 R6 1111111101101111 R7 Advantage • Doesn't consume a register for base address B A 16 ADD • Addresses are often stored in memory (i.e., useful) ALU MAR MEMORY MDR Disadvantage 16 Rd • Extra memory operation (and no offset) CSE 240 5-21 CSE 240 5-22 STI (Indirect) Load Effective Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Problem STI 1 0 1 1 SR PCoffset9 • How can we compute address without also LD/ST-ing to it? Register File STI R3 -17 R0 Solution IR 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 R1 9 R2 • Load Effective Address (LEA) instruction R3 0000000000001001 PC 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 SEXT R4 16 R5 16 Idea R6 16 1111111101101111 R7 • LEA computes address just like PC-relative LD/ST • Store address in destination register (not data at that address) B A 16 ADD • Does not access memory ALU MAR MEMORY MDR 16 Rd/Wr • Example: LEA: R1 <- PC + SEXT(IR[8:0])] (Rd) (Wr) CSE 240 5-23 CSE 240 5-24 6 0001 ADD Machine Language 0011 ST 0101 AND LEA Example 0111 STR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1010 LDI 1110 LEA LEA 1 1 1 0 DR PCoffset9 Address Instruction Comments x30F6 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 R1 ← PC-3 (x30F4) Register File LEA R3 -81 R0 x30F7 0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 R2 ← R1 + 14 = x3102 IR 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 1 R1 9 R2 x30F8 0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1 M[PC-5(x30F4)] ← R2 R3 0011111110001000 PC 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 SEXT R4 x30F9 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2 ← 0 16 R5 16 16 R6 R2 R2 + 5 = 5 1111111110101111 R7 x30FA 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 ← M[R1+14] ← R2 B A x30FB 0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0 (M[x3102] ← 5) ADD ALU R3 ← M[M[x30F4]] x30FC 1 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1 (R3 ← M[x3102]) (R3 ← 5) opcode CSE 240 5-25 CSE 240 5-26 Aside: Machine Language Programming Is Hard! Control Instructions Alter the sequence of instructions • Changing the Program Counter (PC) Conditional Branch • Branch taken if a specified condition is true New PC computed relative to current PC • Otherwise, branch not taken PC is unchanged (I.e., points to next sequential instruction) Unconditional Branch (or Jump) • Always changes the PC • Target address computed PC-relative or Base+Offset TRAP (Altair 8800, 1975) • Changes PC to start of OS “service routine” • When routine is done, execution resumes after TRAP CSE 240 5-27 CSE 240 5-28 7 Condition Codes Branch Instruction LC-3 has three 1-bit condition code registers Branch specifies one or more condition codes N -- negative If the specified condition code set, the branch is taken Z -- zero • PC is set to the address specified in the instruction P -- positive (greater than zero) • Like PC-relative mode addressing, target address is specified as offset from current PC (PC + SEXT(IR[8:0])) Set/cleared by instructions that store value to register • Note: Target must be “near” branch instruction • e.g., ADD, AND, NOT, LD, LDR, LDI, LEA, not ST If branch not taken, next instruction (PC+1) is executed.