MicroprocessorMicroprocessor PackagingPackaging The Key Link in the Chain Koushik Banerjee Technical Advisor Assembly Technology Development Intel Corporation 1 MicroprocessorsMicroprocessors 1971 2001 2 GlobalGlobal PackagingPackaging R&DR&D China Shanghai Philippines Cavite Arizona Chandler Malaysia Penang VirtualVirtual ATDATD 3 MainMain R&DR&D facilityfacility inin Chandler,Chandler, AZAZ 4 Computing needs driving complexity First to introduce organic in mainstream CPUs First to introduce flip chip in Intel 486TM Pentium®mainstreamPentium® Pro Pentium® CPUs II Pentium® III Pentium® 4 Itanium® Processor Processor Processor Processor Processor Processor Processor 25 MHz 1.0+ GHz Ceramic Wire-bond To Organic To Flip Chip 5 LookingLooking aheadahead …… ComplexityComplexity andand ChallengesChallenges toto supportsupport Moore’sMoore’s LawLaw 1. Silicon to package interconnect 2. Within package interconnect 3. Power management 4. Adding more functionality GoalGoal :: BringBring technologytechnology innovationinnovation intointo HighHigh volumevolume manufacturingmanufacturing atat aa LOWLOW COSTCOST 6 SiliconSilicon ?? PackagePackage RelationshipRelationship AnatomyAnatomy 101101 Silicon Processor: The “brain” of the computer (generates instructions) Packaging: The rest of the body (Communicates instructions to the outside world, adds protection) NoNo PackagePackage == NoNo ProductProduct !! Great Packaging = Great Products !! Great Packaging = Great Products !! 7 TheThe KeyKey LinkLink inin thethe ChainChain OpportunityOpportunity Transistor-to-Transistor Innovative,Innovative, efficient,efficient, Ckt Blk to Ckt Blk highhigh performance,performance, lowlow-- costcost packagespackages areare aa significantsignificant competitivecompetitive advantageadvantage Chip-to-Package Package- to-Board Board-to-System 8 ExampleExample –– EnablingEnabling CustomCustom solutionssolutions SiliconSilicon EnablerEnabler ValueValue AddAdd :: customcustom solutionssolutions basedbased onon marketmarket segmentsegment 9 BreakingBreaking BarriersBarriers toto Moore’sMoore’s LawLaw 1 Billion K Transistors 1,000,000 100,000 Pentium®4 Processor Pentium® II Processor ® 10,000 Pentium III Processor Pentium® Processor Pentium® Pro Processor 1,000 i486™ Processor 100 i386™ Processor 80286 TheThe NumberNumber ofof TransistorsTransistors PerPer 10 8086 ChipChip will will Double Double Every Every 18 18 MonthsMonths 1 ’75 ’80 ’85 ’90 ’95 ’00 ’05 ’10 ’15 Source: Intel IntegratedIntegrated PackagingPackaging ++ SiliconSilicon TechnologyTechnology developmentdevelopment isis essentialessential 10 ChallengeChallenge ## 11 SiliconSilicon toto packagepackage interconnectinterconnect 11 ApproachingApproaching 10K10K flipflip chipchip bumpsbumps onon aa diedie Flip Chip (C4) interconnect Underfill 10K Silicon Package Number of flip chip bumps 0 Pentium III® ItaniumTM Family Family Pentium 4® Future Family generations DriverDriver ––increasedincreased siliconsilicon functionality functionality 12 SolutionSolution :: AggressiveAggressive BumpBump PitchPitch ScalingScaling toto keepkeep downdown diedie sizesize Solder Bumps Key Challenges : • Plating bumps • Chip Attach Process • Underfill Human • Joint integrity Hair • HVM scalable process Strand 13 Which leads us to … ChallengeChallenge ## 22 WithinWithin packagepackage InterconnectInterconnect 14 SolutionSolution :: HighHigh DensityDensity InterconnectInterconnect Very high escape routing density from the die Package Traces Lines narrower DriverDriver :: NeedNeed highhigh wiringwiring than hair densitydensity Human Hair 15 DimensionalDimensional StackStack--UpUp Line in Silicon 130 nm (100X magnification) Line in Package 25 um (100X magnification) Line in Motherboard 5 mils (0.005”) (100X magnification) 16 ApproachingApproaching 40K40K micromicro viasvias insideinside aa packagepackage Chip Attach 40K Micro-vias Pads vias in package - 0 # of micro Pentium III® ItaniumTM Package X-section Family Family Pentium 4® Future Family generations DriverDriver ––HighHigh I/OI/O countcount && powerpower supply supply 17 SolutionSolution :: AdvancedAdvanced lithographylithography (new term in packaging !) C/A pads Wire Key Challenges : • Developing HDI (high density interconnect) at LOW COST • High Volume Manufacturing Capable Via Build-Up dielectric Core 18 CoreCore frequencyfrequency trendtrend …… doublingdoubling everyevery 22 yearsyears 100,000 10,000 1,000 Frequency 100 P6 (MHz) Pentium® proc 486 10 8085 386 8086 286 1 8080 8008 0.1 4004 ’70 ’80 ’90 ’00 ’10 Source : Intel Architecture Labs InIn additionaddition …… 19 FSBFSB frequencyfrequency rampramp continuescontinues 400 133 66 Max Mega transfers / second Pentium® II Pentium® III Pentium® 4 Processor Processor Processor Future Generation Processors Microprocessor Generation 20 SolutionSolution :: HighHigh PerformancePerformance InterconnectInterconnect TechnologyTechnology BenefitsBenefits ofof organicorganic 1. Copper – Low resistance 2. Low dielectric constant 3. Cheaper High Performance Silicon Copper Interconnects KeyKey ChallengeChallenge :: ? Optimize the entire substrate architecture (material properties, layer stack-up, via placement, power bussing etc.) Organic Packaging 21 SolutionSolution :: BetterBetter designsdesigns A poor design can ruin processor performance Key Challenges : ? Signal Timing ? Innovative routing – layout ? Optimizing power / ground distribution ? Co-design of the complete silicon ? package interconnect 22 Switching gears from interconnect to … ChallengeChallenge ## 33 PowerPower ManagementManagement 23 PowerPower Increasing,Increasing, siliconsilicon gettinggetting smallersmaller Pentium® Power 100 processors (Watts) 286 486 8086 10 386 8085 8080 8008 1 4004 0.1 ’71 ’74 ’78 ’85 ’92 ’00 ’04 ’08 Source : Intel Architecture Labs Two Challenges … Getting power in & getting heat out 24 ImportanceImportance ofof aa quietquiet PowerPower SupplySupply High Low Ideal state High Low Reality – noise OR High Low OR This is what Voltage Scaling can do 25 NeedNeed lotslots ofof charge,charge, veryvery quicklyquickly …… Increasing distance from supply Hot Water Inefficient Heater design Still Waiting !! Close Proximity to supply 26 SolutionSolution :: OptimizeOptimize designdesign forfor powerpower deliverydelivery KeyKey Challenge:Challenge: ?2X improvement in Cpkg capacitance and Lpkg inductance needed / generation lpkg (pH) Cpkg (uF) ?Need to optimize the complete silicon ? package integrated 0.18 um Future power delivery Generation Generation processors 130 nm processors solution Generation processors 27 SolutionSolution :: ReduceReduce systemsystem designdesign burdenburden –– heatheat removalremoval Temp – Package Temp – Silicon Case (Tc) Temp – Ambient (Tj) (Ta) Temperature Gradient OEM Packaging Provide Solutions Provide Solutions for this interface for this interface of the budget of the budget IntegratedIntegrated ThermalThermal SolutionsSolutions inin thethe packagepackage reducereduce heatheat fluxflux ––easiereasier toto coolcool inin thethe systemsystem 28 ExampleExample :: Pentium4Pentium4® High conductivity Thermal Interface Integrated High Material Conductivity Heat Spreader 29 ExampleExample :: ItaniumItanium® SchematicSchematic ofof howhow aa typicaltypical heatheat pipepipe worksworks Water Vapor Wick Structure Heater Block Vapor Condenses Cooler Section Evaporation Integrated heat pipe Of Heat Pipe Cooler Section technology interfacing Of Heat Pipe directly to the Heat Source Condensed water flows back silicon through the wick structure by capillary action 30 And finally … ChallengeChallenge ## 44 AddingAdding moremore functionalityfunctionality 31 SolutionSolution :: HighHigh DensityDensity interconnectinterconnect == moremore integrationintegration High Density Interconnect enables a large cache memory integration in a small space Leveraging packaging instead of adding onto silicon 32 SolutionSolution :: MassiveMassive integrationintegration == moremore featuresfeatures On CPU Voltage regulation RASM 33 InIn SummarySummary …… 34 WeWe talkedtalked aboutabout futurefuture ComplexityComplexity andand ChallengesChallenges toto supportsupport Moore’sMoore’s LawLaw 1. Silicon to package interconnect 2. Within package interconnect 3. Power management 4. Adding more functionality Intel’sIntel’s PackagingPackaging StrategyStrategy Innovative Technology Making Technology Affordable Smart designs Integrated silicon + packaging solutions 35 For more information, please visit …. http://www.intel.com/research/silicon/packaging.htm http://developer.intel.com/technology/itj/ Search for packaging articles 36.