Freescale Semiconductor, Inc. MPC60XBUSRM 1/2004 Rev. 0.1 . c n I , r o t c u d n o c i PowerPC™ Microprocessor m e S Family: e l a c The Bus Interface for 32-Bit s e Microprocessors e r F For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor,Inc. F o r M o r G e o I n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , Freescale Semiconductor, Inc. Overview 1 Signal Descriptions 2 Memory Access Protocol 3 Memory Coherency 4 . System Status Signals 5 . c n I Additional Bus Configurations 6 , r o t Direct-Store Interface 7 c u d n System Considerations 8 o c i m Processor Summary A e S e Processor Clocking Overview B l a c s Processor Upgrade Suggestions C e e r F L2 Considerations for the PowerPC 604 Processor D Coherency Action Tables E Glossary of Terms and Abbreviations GLO Index IND For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1 Overview 2 Signal Descriptions 3 Memory Access Protocol 4 Memory Coherency . 5 System Status Signals . c n I 6 Additional Bus Configurations , r o t 7 Direct-Store Interface c u d n 8 System Considerations o c i m A Processor Summary e S e B Processor Clocking Overview l a c s C Processor Upgrade Suggestions e e r F D L2 Considerations for the PowerPC 604 Processor E Coherency Action Tables GLO Glossary of Terms and Abbreviations IND Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Contents SectionParagraph Page Number Title Number Table of Contents About This Document . Audience ............................................................................................................ xviii c Organization....................................................................................................... xviii n I Suggested Reading............................................................................................... xix , General Information..................................................................................... xix r PowerPC Documentation...............................................................................xx o t Conventions ........................................................................................................ xxii c Acronyms and Abbreviations ............................................................................ xxiii u d Chapter 1 n o Overview c i 1.1 PowerPC 60x Microprocessor Interface .............................................................. 1-1 m 1.2 PowerPC System Block Diagram ........................................................................ 1-3 e 1.3 Processor Bus Features ........................................................................................ 1-3 S 1.4 Bus Interface Signals ........................................................................................... 1-4 e l a Chapter 2 c Signal Descriptions s e 2.1 Address Bus Arbitration Signals.......................................................................... 2-2 e 2.1.1 Bus Request (BR)—Output ............................................................................. 2-2 r F 2.1.2 Bus Grant (BG)—Input ................................................................................... 2-2 2.1.3 Address Bus Busy (ABB)—Output................................................................. 2-3 2.1.4 Address Bus Busy (ABB)—Input.................................................................... 2-4 2.2 Address Transfer Start Signals............................................................................. 2-4 2.2.1 Transfer Start (TS)—Output ............................................................................ 2-4 2.2.2 Transfer Start (TS)—Input............................................................................... 2-5 2.2.3 Extended Address Transfer Start (XATS)—Output (Direct-Store) ................. 2-5 2.2.4 Extended Address Transfer Start (XATS)—Input (Direct-Store).................... 2-5 2.3 Address Transfer Signals ..................................................................................... 2-6 2.3.1 Address Bus (A[0–31])—Output (Memory Operations)................................. 2-6 2.3.2 Address Bus (A[0–31])—Input (Memory Operations) ................................... 2-6 Contents v For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Contents Paragraph Page Number Title Number 2.3.3 Address Bus (A[0–31])—Output (Direct-Store Operations)........................... 2-7 2.3.4 Address Bus (A[0–31])—Input (Direct-Store Operations) ............................. 2-7 2.3.5 Address Bus Parity (AP[0–3])—Output.......................................................... 2-7 2.3.6 Address Bus Parity (AP[0–3])—Input............................................................. 2-8 2.3.7 Address Parity Error (APE)—Output.............................................................. 2-8 2.4 Address Transfer Attribute Signals...................................................................... 2-8 2.4.1 Transfer Type (TT[0–4])—Output................................................................... 2-9 2.4.2 Transfer Type (TT[0–4])—Input ..................................................................... 2-9 . 2.4.3 Transfer Burst (TBST)—Output.................................................................... 2-10 . 2.4.4 Transfer Burst (TBST)—Input ...................................................................... 2-11 c 2.4.5 Transfer Size (TSIZ[0–2])—Output .............................................................. 2-11 n 2.4.6 Transfer Size (TSIZ[0–2])—Input................................................................. 2-12 I , 2.4.7 Transfer Code (TCn)—Output....................................................................... 2-12 r 2.4.8 Cache Inhibit (CI)—Output........................................................................... 2-16 o t 2.4.9 Write-Through (WT)—Output ...................................................................... 2-17 c 2.4.10 Global (GBL)—Output.................................................................................. 2-17 u 2.4.11 Global (GBL)—Input .................................................................................... 2-17 d 2.4.12 Cache Set Element (CSEn)—Output............................................................. 2-18 n 2.4.13 High-Priority Snoop Request (HP_SNP_REQ)–601 Only............................ 2-18 o 2.5 Address Transfer Termination Signals............................................................... 2-18 c i 2.5.1 Address Acknowledge (AACK)—Input........................................................ 2-18 m 2.5.2 Address Retry (ARTRY)—Output................................................................. 2-19 e 2.5.3 Address Retry (ARTRY)—Input ................................................................... 2-20 S 2.5.4 Shared (SHD)—Output.................................................................................. 2-20 e 2.5.5 Shared (SHD)—Input .................................................................................... 2-20 l 2.6 Data Bus Arbitration Signals ............................................................................. 2-21 a c 2.6.1 Data Bus Grant (DBG)—Input...................................................................... 2-21 s 2.6.2 Data Bus Write Only (DBWO)—Input ......................................................... 2-22 e 2.6.3 Data Bus Busy (DBB)—Output .................................................................... 2-23 e 2.6.4 Data Bus Busy (DBB)—Input ....................................................................... 2-23 r F 2.7 Data Transfer Signals......................................................................................... 2-23 2.7.1 Data Bus (DH[0–31], DL[0–31])—Output ................................................... 2-24 2.7.2 Data Bus (DH[0–31], DL[0–31])—Input ...................................................... 2-24 2.7.3 Data Bus Parity (DP[0–7])—Output.............................................................. 2-25 2.7.4 Data Bus Parity (DP[0–7])—Input ................................................................ 2-26 2.7.5 Data Parity Error (DPE)—Output.................................................................. 2-26 2.7.6 Data Bus Disable (DBDIS)—Input ............................................................... 2-26 2.8 Data Transfer Termination Signals .................................................................... 2-27 2.8.1 Transfer Acknowledge (TA)—Input.............................................................. 2-27 2.8.2 Data Retry (DRTRY)—Input......................................................................... 2-27 2.8.3 Transfer Error Acknowledge (TEA)—Input ................................................. 2-28 PowerPC™ Microprocessors: Bus Interface for 32-Bit Microprocessors For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Contents Paragraph Page Number Title Number 2.9 System Status Signals ........................................................................................ 2-29 2.9.1 Interrupt (INT)—Input................................................................................... 2-29 2.9.2 System Management Interrupt (SMI)—Input................................................ 2-29 2.9.3 Machine Check Interrupt (MCP)—Input....................................................... 2-30