ARM Debugger TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents ...................................................................................................................... ICD In-Circuit Debugger ................................................................................................................ Processor Architecture Manuals .............................................................................................. ARM/CORTEX/XSCALE ........................................................................................................... ARM Debugger ..................................................................................................................... 1 History ................................................................................................................................ 7 Warning .............................................................................................................................. 8 Introduction ....................................................................................................................... 9 Brief Overview of Documents for New Users 9 Demo and Start-up Scripts 10 Quick Start of the JTAG Debugger .................................................................................. 12 FAQ ..................................................................................................................................... 13 Troubleshooting ................................................................................................................ 14 Communication between Debugger and Processor cannot be established 14 Trace Extensions ............................................................................................................... 15 Symmetric Multiprocessing ............................................................................................. 16 ARM Specific Implementations ........................................................................................ 17 TrustZone Technology 17 Debug Permission 17 Checking Debug Permission 18 Checking Secure State 18 Changing the Secure State from within TRACE32 18 Accessing Memory 18 Accessing Coprocessor CP15 Register 19 Accessing Cache and TLB Contents 19 Breakpoints and Vector Catch Register 19 Breakpoints and Secure Modes 19 big.LITTLE 20 Debugger Setup 20 Consequence for Debugging 21 Requirements for the Target Software 21 ©1989-2021 Lauterbach GmbH ARM Debugger 1 big.LITTLE MP 21 Breakpoints 22 Software Breakpoints 22 On-chip Breakpoints for Instructions 22 On-chip Breakpoints for Data 22 Hardware Breakpoints (Bus Trace only) 24 Example for Standard Breakpoints 25 Complex Breakpoints 31 Direct ICE Breaker Access 31 Example for ETM Stopping Breakpoints 32 Access Classes 33 Coprocessors 41 Accessing Memory at Run-time 43 Semihosting 47 SVC (SWI) Emulation Mode 47 DCC Communication Mode (DCC = Debug Communication Channel) 49 Virtual Terminal 51 Large Physical Address Extension (LPAE) 52 Consequence for Debugging 52 Virtualization Extension, Hypervisor 53 Consequence for Debugging 53 Run-time Measurements 53 Trigger 53 ARM specific SYStem Commands ...................................................................................54 SYStem.CLOCK Inform debugger about core clock 54 SYStem.CONFIG.state Display target configuration 54 SYStem.CONFIG Configure debugger according to target topology 55 <parameters> describing the “DebugPort” 63 <parameters> describing the “JTAG” scan chain and signal behavior 68 <parameters> describing a system level TAP “Multitap” 72 <parameters> configuring a CoreSight Debug Access Port “DAP” 74 <parameters> describing debug and trace “Components” 78 <parameters> which are “Deprecated” 89 SYStem.CONFIG.EXTWDTDIS Disable external watchdog 94 SYStem.CONFIG SMMU Internal use 95 SYStem.CPU Select the used CPU 97 SYStem.JtagClock Define the frequency of the debug port 97 SYStem.LOCK Tristate the JTAG port 100 SYStem.MemAccess Run-time memory access 101 SYStem.Mode Establish the communication with the target 107 SYStem.Option Special setup 110 SYStem.Option ABORTFIX Do not access memory area from 0x0 to 0x1f 110 SYStem.Option AHBHPROT Select AHB-AP HPROT bits 110 ©1989-2021 Lauterbach GmbH ARM Debugger 2 SYStem.Option AMBA Select AMBA bus mode 110 SYStem.Option ASYNCBREAKFIX Asynchronous break bugfix 111 SYStem.Option AXIACEEnable ACE enable flag of the AXI-AP 111 SYStem.Option AXICACHEFLAGS Select AXI-AP CACHE bits 111 SYStem.Option AXIHPROT Select AXI-AP HPROT bits 112 SYStem.Option BUGFIX Breakpoint bug fix 112 SYStem.Option BUGFIXV4 Asynch. break bug fix for ARM7TDMI-S REV4 113 SYStem.Option BigEndian Define byte order (endianness) 114 SYStem.Option BOOTMODE Define boot mode 114 SYStem.Option CINV Invalidate the cache after memory modification 115 SYStem.Option CFLUSH FLUSH the cache before step/go 115 SYStem.Option CacheParam Define external cache 115 SYStem.Option CorePowerDetection Set methods to detect core power 115 SYStem.Option DACRBYPASS Ignore DACR access permission settings 117 SYStem.Option DAPDBGPWRUPREQ Force debug power in DAP 117 SYStem.Option DAP2DBGPWRUPREQ Force debug power in DAP2 118 SYStem.Option DAPSYSPWRUPREQ Force system power in DAP 118 SYStem.Option DAP2SYSPWRUPREQ Force system power in DAP2 119 SYStem.Option DAPNOIRCHECK No DAP instruction register check 120 SYStem.Option DAPREMAP Rearrange DAP memory map 120 SYStem.Option DBGACK DBGACK active on debugger memory accesses 120 SYStem.Option DBGNOPWRDWN DSCR bit 9 will be set in debug mode 121 SYStem.Option DBGUNLOCK Unlock debug register via OSLAR 121 SYStem.Option DCDIRTY Bugfix for erroneously cleared dirty bits 121 SYStem.Option DCFREEZE Disable data cache linefill in debug mode 122 SYStem.Option DEBUGPORTOptions Options for debug port handling 122 SYStem.Option DIAG Activate more log messages 123 SYStem.Option DisMode Define disassembler mode 124 SYStem.Option DynVector Dynamic trap vector interpretation 125 SYStem.Option EnReset Allow the debugger to drive nRESET (nSRST) 125 SYStem.Option ETBFIXMarvell Read out on-chip trace data 125 SYStem.Option ETMFIX Shift data of ETM scan chain by one 126 SYStem.Option ETMFIXWO Bugfix for write-only ETM register 126 SYStem.Option ETMFIX4 Use only every fourth ETM data package 126 SYStem.Option EXEC EXEC signal can be used by bustrace 126 SYStem.Option EXTBYPASS Switch off the fake TAP mechanism 127 SYStem.Option FASTBREAKDETECTION Fast core halt detection 127 SYStem.Option HRCWOVerRide Enable override mechanism 127 SYStem.Option ICEBreakerETMFIXMarvell Lock on-chip breakpoints 128 SYStem.Option ICEPICK Enable/disable assertions and wait-in-reset 128 SYStem.Option IMASKASM Disable interrupts while single stepping 128 SYStem.Option IMASKHLL Disable interrupts while HLL single stepping 129 SYStem.Option INTDIS Disable all interrupts 129 ©1989-2021 Lauterbach GmbH ARM Debugger 3 SYStem.Option IRQBREAKFIX Break bugfix by using IRQ 129 SYStem.Option KEYCODE Define key code to unsecure processor 130 SYStem.Option L2Cache L2 cache used 130 SYStem.Option L2CacheBase Define base address of L2 cache register 130 SYStem.Option LOCKRES Go to 'Test-Logic Reset' when locked 131 SYStem.Option MACHINESPACES Address extension for guest OSes 132 SYStem.Option MEMORYHPROT Select memory-AP HPROT bits 133 SYStem.Option MemStatusCheck Check status bits during memory access 133 SYStem.Option MMUPhysLogMemaccess Memory access preferences 133 SYStem.Option MMUSPACES Separate address spaces by space IDs 134 SYStem.Option MonitorHoldoffTime Delay between monitor accesses 135 SYStem.Option MPUBYPASS Ignore MPU access permission settings 135 SYStem.Option MultiplesFIX No multiple loads/stores 135 SYStem.Option NODATA No data connected to the trace 135 SYStem.Option NOIRCHECK No JTAG instruction register check 136 SYStem.Option NoPRCRReset Do not cause reset by PRCR 136 SYStem.Option NoRunCheck No check of the running state 136 SYStem.Option NoSecureFix Do not switch to secure mode 137 SYStem.Option OVERLAY Enable overlay support 138 SYStem.Option PALLADIUM Extend debugger timeout 138 SYStem.Option PC Define address for dummy fetches 139 SYStem.Option PROTECTION Sends an unsecure sequence to the core 139 SYStem.Option PWRCHECK Check power and clock 139 SYStem.Option PWRCHECKFIX Check power and clock 140 SYStem.Option PWRDWN Allow power-down mode 140 SYStem.Option PWRDWNRecover Mode to handle special power recovery 141 SYStem.Option PWRDWNRecoverTimeOut Timeout for power recovery 141 SYStem.Option PWROVR Specifies power override bit 141 SYStem.Option ResBreak Halt the core after reset 142 SYStem.Option ResetDetection Choose method to detect a target reset 143 SYStem.Option RESetREGister Generic software reset 143 SYStem.Option RESTARTFIX Wait after core restart 144 SYStem.Option RisingTDO Target outputs TDO on rising edge 144 SYStem.Option ShowError Show data abort errors 145 SYStem.Option SOFTLONG Use 32-bit access to set breakpoint 145 SYStem.Option SOFTQUAD Use 64-bit access to set breakpoint 145 SYStem.Option SOFTWORD Use 16-bit access to set breakpoint 146 SYStem.Option SPLIT Access memory depending on CPSR 146 SYStem.Option StandByTraceDelaytime Trace activation after reset 146 SYStem.Option STEPSOFT Use software breakpoints for ASM stepping 146 SYStem.Option SYSPWRUPREQ Force system power 147 SYStem.Option TIDBGEN Activate initialization for TI derivatives 147 SYStem.Option TIETMFIX Bug fix for customer specific ASIC 147 ©1989-2021 Lauterbach GmbH ARM Debugger 4 SYStem.Option TIDEMUXFIX Bug fix for customer