Silicon Photonics: A Platform for Integration, Wafer Level Assembly and Packaging M. Asghari Kotura Inc April 2007 Contents: ► Who is Kotura ► Choice of waveguide technology ► Challenges and merits of Si photonics packaging Integration: High functionality and lower component count Fibre interface Stress related issues Thermal management Hybrid assembly ► Examples of current activities 2 Who is Kotura? ► Founded in 2003: Merger of two companies ► A Leading Silicon Photonics Company Shipping in volume to Tier-1 customers Products deployed in live networks Over 50 patents issued / pending and license to all Bookham Si based IP. ► Strategy based on partnership Build competence on chip design and fabrication Be a high value, high functionality chip supplier Form partnerships for product development, fast market penetration and achieving maximum application coverage ► In house Si Fab, prototype packaging and low volume A&T 0.25um DUV Scanner, World Class Dry Etch Capability, ... ► Sub Con manufacturing partner in China ► Happy to work as partner / foundry on a joint development or sub-contract basis 3 Si Technology: Basics Waveguide width Key Strengths Silicon Ridge - Manufacturability thickness height -Scalability Si - Volume cost curve Oxide - Process control Si substrate - Potential for integration - Solid state reliability - Electronic integration - Full set of functionality Material Property Si Passive devices 3.47 Refractive Index Current injection devices Well controlled Detectors, VOAs etc Material Type Crystal Hybridisation capability dn / dT 1.8x10-4K-1 Thermal Conductivity, 130-156 W/mK Key Challenges K - Fibre interface Tuning 85 pm / oC - Temperature control o - Stress issues on packaging Temp Stability + / - 0.1 C 4 Choice of Waveguide Technology 100 Experimental data 100 10 Propagation Loss 10 (dB/cm) Deep etch 1 technology 1 Bend Radius (mm) Bend Radius (mm) 0.1 0.1 Propagation Loss (dB/cm) Photonics sweet Waveguide Dimension (um) spot 0.01 0.01 0.1 1 10 Kotura Electronics III/V Fiber 5 Choice of Waveguide Technology 0 ► Propagation loss independent of Wavelength Propagation Loss (dB) TE(dB/cm) and Polarization 3um Core Waveguide TM(dB/cm) ► Very low group velocity and polarization mode -0.1 dispersion Experimental ► Very low waveguide crossing loss and X-talk -0.2 ► Optimum core size for most optical functionalities is at 3 to 4um. Wavelength (nm) -0.3 0 0 3 1520 1530 1540 1550 1560 1570 XTalk_TE(0.5um) 1 Loss XTalk_TE(1um) -20 0.3 XTalk_TE(3um) 0.5 H Loss_TE(0.5um) Group index TE Loss_TM(0.5um) TM 4 -40 0.6 Loss_TE(1um) Loss_TM(1um) 0.5 Loss_TE(3um) -60 0.9 Loss_TM(3um) Effective index 3 1 H 3 TE TM -80 1.2 Loss (dB) Theoretical 2 Effect and group index and Effect Crosstalk (dB) X-Talk -100 1.5 0.5 1 1.5 2 2.5 -120 1.8 WG Thickness (um) 012345678910 Waveguide Width, W ( um) 6 Passive Waveguide Technology 0 Key Components -5 Bends and Mirrors Couplers and splitters -10 Mode transformers -15 Wavelength Mux / Demux / -20 selective elements Polarisation splitters, rotators Transmission (dB) -25 and discriminators -30 Optical / modal Filters -35 <0.1dB Loss for -40 U-bend with Part 1 191.8 192.3 192.8 193.3 193.8 194.3 194.8 195.3 195.8 Part 2 Frequency (THz) 250um Radius Part 3 500 400 300 R 200 100 NumberCombinations. of 0 22--24 24--26 26--28 32--34 28--30 30--32 34--36 36--38 46--48 52--54 54--56 56--58 48--50 50--52 38--40 40--42 42--44 44--46 Intra-channel Crosstalk (dB) 7 Current Injection Devices: VOA example 1 n-type 0.9 0.8 p-type 0.7 0.6 Silica 400mW 0.5 p+ n+ 0.4 SOI Thermal BOX Thick BOX 0.3 40mW SOI - Carrier 0.2 Silicon injection 10 mW SOI Thermal Thin Normalised phase change Normalised 0.1 BOX 400mW Time (ms) 50 0 0.0001 0.001 0.01 0.1 1 10 45 40 0 -2 35 -4 MZ switch -6 30 7 -8 6 -10 25 5 -12 Attenuation (dB) Attenuation -14 20 4 Extinction / dB -16 (units of Pi) of (units 15 3 Phase Shift -18 Bar TE Cross TE 2 -20 Bar TM Cross TM 10 -22 1 0 5 10 15 20 25 30 35 40 5 Attenuation (dB) 0 Applied Current / mA Current (mA) 0246810 0 0 5 10 15 20 25 30 35 40 458 50 III/V Device Hybridization Laser / SOA Hybridization Shelf on which the laser is mounted wirebond Solder Metal track Commodity actives for low Solder Si Metalization Vertical plinth cost Accurate vertical alignment is achieved by removing low tolerance layers from the laser and accurate etching in Si of mounting shelf Alignment marks aim to achieve maximum lateral placement accuracy Si plated with solder and includes some simple electronics components Si Waveguide On placement of laser local heating is applied to reflow the solder Photo-diode Hybridization High Resisitivity Si for RF Lines Horizontal taper in Si can improve lateral coupling loss due to lateral placement in-accuracies Waveguide Mirror 9 Fiber Coupling Kotura’s Patented Epi Taper 1um to 4um core technology enables: - Fiber mode matching with no compromise in device performance 12um core - Core size reduction evolution • A three dimensional taper (mode expander) reduces coupling loss to <0.5dB. • The back reflection from such a facet is <-50dB • PDL is <0.05dB • Wavelength and Temperature insensitive • Technology offers low cost passive V- groove based fibre attach Vertical Fibre position (um) 20 30 40 50 60 70 -30 3D Taper -40 -50 -60 Back Reflection -65dB -70 10 Stress Management Challenges: Stress induced ► Si is prone to stress induced x & y index index change change ► This can cause polarization conversion, polarization mode dispersion and PDL ~0.0% TM Strain not ► A combination of stress and included roughness can also cause mode conversion Strain included Ex field Ey field Typically 0.1% TM Ex field Ey field Stress and roughness can cause mode conversion 11 Stress Management 3.5 PDF Benefits 3 (GHz) ► Stress can be used for performance 2.5 correction eg on AWG array for PDF. 2 ► Stress can be utilized for sensor 1.5 applications 1 0.5 Channel 0 Before PDF Compensation 010203040 -6 -6.5 -7 -7.5 -8 -8.5 -9 -9.5 -10 -10.5 -11 -11.5 -12 191.8 191.85 191.9 191.95 192 192.05 192.1 192.15 192.2 192.25 192.3 192.35 192.4 192.45 192.5 192.55 192.6 192.65 192.7 192.75 192.8 192.85 19 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 -8.5 -9 -9.5 -10 -10.5 192.8 192.85 192.9 192.95 193 193.05 193.1 193.15 193.2 193.25 193.3 193.35 193.4 193.45 193.5 193.55 193.6 193.65 193.7 193.75 193.8 193.85 19 After PDF Compensation 12 Thermal Considerations 10 channel VOA ► High Si dn/dT requires a high level of thermal stability Temp differential on chip, DT = 0.38 oC ► High thermal conductivity of Si 3 channels on enables excellent temperature uniformity and effective heat removal ► Developments in Si packaging have o enabled better than 0.1oC thermal 9 channels on DT = 0.37 C management even with high power and time varying thermal dissipation 600 Improvements made in at chip level. thermal management of Si 400 PLCs ► Integrated temperature sensors can be fabricated into the fabric of the Si 200 chip close to sensitive areas -10 0 10 20 30 0 40 50 60 70 2500 / pm Grid Offset Resistance (Ohms) nin: 0.5% °C-1, pip: 0.7%°C-1 -200 2000 -400 Ambient Temperature / DegC Temperature (deg C) -600 0 100 20 30 40 50 60 70 80 13 Thermal Considerations …. ► Thermal isolation features such as deep etches and bridge structures can be fabricated to enable thermal Thermal isolation trench isolation 4 Wavelength Shift (nm) 3 DFB (0.1) ► Si and InP based 2 DFB(0.08) devices have very 1 AWG (Si) similar wavelength AWG (SiO2) drift with 0 temperature 0 10203040506070 -1 -2 -3 Temperature (C) -4 14 Si Integrates Waveguides and Micro-Bench Capabilities Front Facet Monitor p n + + BOX VOAs Passive Fiber Laser: Passive Attach Auto-aligned Grating or WDM Coupler Developed in collaboration with Enablence Monitor VOA Laser Surface Mount PD Active WDM Coupler PIN area WDM Coupler VOA APD - Wafer scale testing Future Development - Flip chip technology for fiber attach 15 100Ge CWDM Solution Tx ► 10 CWDM DFB Lasers hybridized into the Si chip either individually or as a bar ► Integrated AWG or Echelle grating, to Mux channels together Lasers Detectors ► Lasers directly modulated ► Front facet detectors integrated to provide power monitoring ► VOAs can be integrated to provide power 6.5nm 12nm balancing without the need to modify laser drive conditions Rx ► Individual PINs or a bar, surface mounted onto wet etched 54 degree vertical coupling mirrors. DFB λ registration: +/- 2nm ► Demux is integrated into the same chip ► Fast VOAs can be integrated to improve dynamic range or provide protection 16 Kotura’s CWDM 100Ge Solution - High level of integration both monolithic Active area (waveguide) and hybrid (micro-bench) - Developed in partnership with Cyoptcis into a very small form factor package PD / Surface mount technology Au:Sn solder 7mm 15mm Monitor / VOAs p+ n+ Mux / WDM DFB Array DeMux (Cyoptics) BOX VOAs 17 Fitting 100G into ~10G Footprint ! Micro-bench assembly ux x M + u + De M & 10 x 10G 10 x 10G ROSAs TOSAs Conventional technology can not support the footprint Or 100G TOSA Si PLC Tx Chip 100Ge TxRx Si PLC Rx Chip 100G ROSA Si Solution can support 10G FXP footprint for 100G and offers huge 100Ge Module cost saving potential 18 Key Challenges & Merits Ceramic ► Key Challenges Carrier Low propagation and fiber coupling loss Facet preparation Si AWG Optical, Electrical & Thermal X-talk Low stress chip attach Thermal management Fiber Lead frame Block ► Key merits Low component count: Integration Low cost fiber attach: V-groove Stress engineering for compensation Thermal tuning Excellent thermal conductivity