Principles of VLSI Design CMOS Basics CMPE 413 MOS: Metal Oxide Semiconductor Transistors are built on a Silicon (semiconductor) substrate. Pure silicon has no free carriers and conducts poorly. Dopants are added to increase conductivity: extra electrons (n-type) or extra holes (p-type) MOS structure created by superimposing several layers of conducting, insulating and tran- sistor-forming materials. Metal gate has been replaced by polysilicon or poly in modern technologies. There are two types of MOS transistors: nMOS : Negatively doped silicon, rich in electrons. pMOS : Positively doped silicon, rich in holes. CMOS: Both type of transistors are used to construct any gate. 1 Principles of VLSI Design CMOS Basics CMPE 413 nMOS and pMOS Four terminal devices: Source, Gate, Drain, body (substrate, bulk). SourceGate Drain Polysilicon Thin W Oxide SiO2 Source Gate Drain L nMOS n+ n+ n+ p bulk Si p substrate n+ SourceGate Drain Polysilicon SiO2 pMOS p+ p+ n bulk Si 2 Principles of VLSI Design CMOS Basics CMPE 413 CMOS Inverter Cross-Section Cadence Layer's for AMI 0.6mm technology m1-m2 contact (via) p-diffusion contact (cc) p-substrate contact (cc) (source) metal2 metal1 n-diffusion contact (cc) n-substrate contact (cc) (source) (Out) glass(insulator) VDD GND layer #3 layer #2 layer #1 p+ n+ n+ p+ p+ n+ (pactive) (drains) n-well (nwell) (nactive) p substrate (black background) n-transistor polysilicon gate (poly ) p-transistor 3 Principles of VLSI Design CMOS Basics CMPE 413 CMOS Cadence Layout Cadence Layout for the inverter on previous slide 4 Principles of VLSI Design CMOS Basics CMPE 413 MOS Transistor Switches We can treat MOS transistors as simple on-off switches with a source (S), gate (G) (con- trols the state of the switch) and drain (D). 1 represents high voltage, VDD (5V, 3.3V, 1.8V, 1.2V, <=1.0V today, .....) 0 represent low voltage - GND or VSS. (0V for digital circuits) g = 0 g = 1 d d d OFF nMOS g ON s s s d d d OFF pMOS g ON s s s 5 Principles of VLSI Design CMOS Basics CMPE 413 Signal Strengths Signals such as 1 and 0 have strengths, measures ability to sink or source current VDD and GND Rails are the strongest 1 and 0 Under the switch abstraction, G has complete control and S and D have no effect. In reality, the gate can turn the switch on only if a potential difference of at least Vt exists between the G and S. We will look at Vt in detail later on in the course. Thus signal strengths are related to Vt and therefore p and n transistors produce signals with different strengths Strong 1: VDD, Strong 0: GND, Weak 1 :(~VDD -Vt) and Weak 0 :(~GND + Vt). G 1 nMOS1 G 0 pMOS 0 SD SD 0 1 0 1 *** Strong 0*** Weak 1 Weak 0 *** Strong 1*** 6 Principles of VLSI Design CMOS Basics CMPE 413 CMOS Inverter Vdd A O P1 AOut A O N1 0 1 1 0 CMOS Inverter THE CONFIGURATION BELOW FOR A BUFFER IS NOT A GOOD IDEA. WHY? A Vdd P1 N1 BAD IDEA Out 7 Principles of VLSI Design CMOS Basics CMPE 413 NAND and NOR CMOS Gates Vdd ABC A A B C P1 P2 B 00 1 Out 01 1 N2 10 1 11 N1 0 Vdd A ABC P1 A C B 00 1 P2 B Out 01 0 10 0 N1 N2 110 8 Principles of VLSI Design CMOS Basics CMPE 413 Pass Transistor The off-state of a transistor creates a high impedance condition Z at the drain. No current flows from source to drain. So transistors can be used as switches. g g = 0 Inputg = 1 Output sd 0 strong 0 sd g = 1 g = 1 sd 1 degraded 1 g = 0 Input Output g g = 0 sd 0 degraded 0 sd g = 1 g = 0 sd strong 1 However, as we previously discussed this will produce degraded outputs, if only one transistor is used as a switch. 9 Principles of VLSI Design CMOS Basics CMPE 413 Transmission Gates A One pMOS and one nMOS in parallel. P1 Note that neither transistor is connected to VDD or GND. In Out N1 A and A control the transmission of a signal on In to Out. A Transmission gates act as tristate buffers. Input Output g = 0, gb = 1 g g = 1, gb = 0 ab 0 strong 0 a b g = 1, gb = 0 g = 1, gb = 0 ab strong 1 gb 1 g g g ab ab ab gb gb gb 10 Principles of VLSI Design CMOS Basics CMPE 413 Transmission Gate Application: Select Mux Transmission Gate 2-to-1 MUX Select A In Out Select Out Select B VDD Truth Table for 2-to-1 MUX Select Out Select 0 B 1 A Out = A.S + B.S How many transistors are required to implement this using CMOS gates? 11 Principles of VLSI Design CMOS Basics CMPE 413 D Latch Positive CLK CLK level-sensitive latch D DQ Latch Q CLK CLK Q Q D 1 Q D Q 0 CLK CLK If CLK is unavailable one extra inverter CLK needed to generate it using CLK 12 Principles of VLSI Design CMOS Basics CMPE 413 D Flip-Flop Positive CLK edge-triggered CLK flip-flop a.k.a D master-slave DQ flip-flop Flop Q CLK CLK CLK QM D Q CLK CLK CLK Master CLK CLK Slave QM DQ Latch Latch CLK CLK Master Slave If CLK is unavailable one extra inverter needed to generate it using CLK 13 Principles of VLSI Design CMOS Basics CMPE 413 D Flip-Flop Operation QM D Q QM follows D, Q is latched CLK = 0 QM D Q QM transferred to Q, QM latched CLK = 1 CLK Positive edge-triggered D flip-flop Q 14 Principles of VLSI Design CMOS Basics CMPE 413 More CMOS Gates Vdd B P1 Vdd P2 A Out N2 N1 15 Principles of VLSI Design CMOS Basics CMPE 413 And More CMOS Gates A B Out B 16 Principles of VLSI Design CMOS Basics CMPE 413 And More CMOS Gates Vdd P2 P1 P3 P4 OAI A N1 B N2 C D N3 N4 17.