UM0434 e200z3 PowerPC core Reference manual Introduction The primary objective of this user’s manual is to describe the functionality of the e200z3 embedded microprocessor core for software and hardware developers. This book is intended as a companion to the EREF: A Programmer's Reference Manual for Freescale Book E Processors (hereafter referred to as EREF). Book E is a PowerPC™ architecture definition for embedded processors that ensures binary compatibility with the user-instruction set architecture (UISA) portion of the PowerPC architecture as it was jointly developed by Apple, IBM, and Motorola (referred to as the AIM architecture). This document distinguishes among the three levels of the architectural and implementation definition, as follows: ● The Book E architecture—Book E defines a set of user-level instructions and registers that are drawn from the user instruction set architecture (UISA) portion of the AIM definition PowerPC architecture. Book E also includes numerous supervisor-level registers and instructions as they were defined in the AIM version of the PowerPC architecture for the virtual environment architecture (VEA) and the operating environment architecture (OEA). Because the operating system resources (such as the MMU and interrupts) defined by Book E differ greatly from those defined by the AIM architecture, Book E introduces many new registers and instructions. ● Freescale Book E implementation standards (EIS)—In many cases, the Book E architecture definition provides a general framework, leaving specific details up to the implementation. To ensure consistency among its Book E implementations, Freescale has defined implementation standards that provide an additional layer of architecture between Book E and the actual devices. ● e200z3 implementation details—Each processor typically defines instructions, registers, register fields, and other aspects that are more detailed than either the Book E definition or the EIS. This book describes all of the instructions and registers implemented on the e200z3, including those defined by Book E and by the EIS, as well as those that are e200z3-specific. Information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers’ responsibility to be sure they are using the most recent version of the documentation. Nov 2013 Rev 2 1/391 www.st.com Table of contents UM0434 Table of contents 1 Organization . 20 1.1 Bibliography . 20 1.2 Related documentation . 21 1.3 Audience . 21 2 Conventions . 22 2.1 Terminology conventions . 22 2.2 Acronyms and abbreviations . 23 3 e200z3 core complex overview . 24 3.1 Overview of the e200z3 . 24 3.1.1 Features . 25 3.2 Programming model . 26 3.2.1 Register set . 26 3.3 Instruction set . 27 3.4 VLE APU . 29 3.5 Interrupts and exception handling . 29 3.5.1 Interrupt handling . 29 3.5.2 Interrupt classes . 30 3.5.3 Interrupt types . 30 3.5.4 Interrupt registers . 31 3.6 Microarchitecture summary . 32 3.6.1 Instruction unit features . 34 3.6.2 Integer unit features . 34 3.6.3 Load/Store unit (LSU) features . 34 3.6.4 Memory management unit (MMU) features . 34 3.6.5 System bus (core complex interface) features . 35 3.6.6 Nexus3 module features . 35 3.7 Legacy support of PowerPC architecture . 35 3.7.1 Instruction set compatibility . 35 3.7.2 Memory subsystem . 36 3.7.3 Interrupt handling . 36 3.7.4 Memory management . 36 2/391 UM0434 Table of contents 3.7.5 Reset . 37 3.7.6 Little-endian mode . 37 4 Register model . 38 4.1 PowerPC Book E registers . 39 4.2 e200z3 - Specific registers . 42 4.3 e200z3-Specific Device Control Registers . 43 4.4 Processor control registers . 43 4.4.1 Machine state register (MSR) . 43 4.4.2 Processor ID register (PIR) . 45 4.4.3 Processor version register (PVR) . 45 4.4.4 System version register (SVR) . 46 4.5 Registers for integer operations . 46 4.5.1 General purpose registers (GPRs) . 46 4.5.2 Integer exception register (XER) . 47 4.6 Registers for branch operations . 47 4.6.1 Condition register (CR) . 47 4.6.2 Count register (CTR) . 51 4.6.3 Link register (LR) . 51 4.7 SPE and SPFP APU registers . 52 4.7.1 Signal processing/embedded floating-point status and control register (SPEFSCR) 52 4.7.2 Accumulator (ACC) . 55 4.8 Interrupt Registers . 55 4.8.1 Interrupt Registers Defined by Book E . 56 4.9 Exception syndrome register (ESR) . 59 4.9.1 VLE mode instruction syndrome . 60 4.9.2 Misaligned instruction fetch syndrome . 61 4.9.3 Precise external termination error syndrome . 61 4.9.4 e200z3 specific interrupt registers . 61 4.10 Software use SPRs (SPRG0–SPRG7 and USPRG0) . 63 4.11 Timer registers . 63 4.11.1 Timer control register (TCR) . 64 4.11.2 Timer status register (TSR) . 66 4.11.3 Time base (TBU and TBL) . 67 4.11.4 Decrementer register . 68 3/391 Table of contents UM0434 4.11.5 Decrementer auto-reload register (DECAR) . 69 4.12 Debug registers . 69 4.12.1 Debug address and value registers . 69 4.12.2 Debug counter register (DBCNT) . 70 4.12.3 Debug control and status registers (DBCR0–DBCR3) . 71 4.12.4 Debug status register (DBSR) . 82 4.13 Hardware implementation dependent registers . 84 4.13.1 Hardware implementation dependent register 0 (HID0) . 84 4.13.2 Hardware implementation dependent register 1 (HID1) . 86 4.14 Branch target buffer (BTB) registers . 87 4.14.1 Branch unit control and status register (BUCSR) . 87 4.15 L1 cache configuration registers . 88 4.15.1 L1 cache configuration register 0 (L1CFG0) . 88 4.16 MMU registers . 88 4.16.1 MMU control and status register 0 (MMUCSR0) . 88 4.16.2 MMU configuration register (MMUCFG) . 89 4.16.3 TLB configuration registers (TLBnCFG) . 90 4.16.4 MMU assist registers (MAS0–MAS4, MAS6) . 91 4.16.5 Process ID register (PID0) . ..