Journal of Electrical and Computer Engineering ESL Design Methodology Guest Editors: Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, and Zhiru Zhang ESL Design Methodology Journal of Electrical and Computer Engineering ESL Design Methodology Guest Editors: Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, and Zhiru Zhang Copyright © 2012 Hindawi Publishing Corporation. All rights reserved. This is a special issue published in “Journal of Electrical and Computer Engineering.” All articles are open access articles distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, pro- vided the original work is properly cited. Editorial Board The editorial board of the journal is organized into sections that correspond to the subject areas covered by the journal. Circuits and Systems M. T. Abuelma’atti, Saudi Arabia Yong-Bin Kim, USA Gabriel Robins, USA Ishfaq Ahmad, USA H. Kuntman, Turkey Mohamad Sawan, Canada Dhamin Al-Khalili, Canada Parag K. Lala, USA Raj Senani, India Wael M. Badawy, Canada Shen-Iuan Liu, Taiwan Gianluca Setti, Italy Ivo Barbi, Brazil Bin-Da Liu, Taiwan Jose Silva-Martinez, USA Martin A. Brooke, USA Joao˜ A. Martino, Brazil Nicolas Sklavos, Greece Chip Hong Chang, Singapore Pianki Mazumder, USA Ahmed M. Soliman, Egypt Y. W. Chang, Taiwan Michel Nakhla, Canada Dimitrios Soudris, Greece Tian-Sheuan Chang, Taiwan Sing K. Nguang, New Zealand Charles E. Stroud, USA Tzi-Dar Chiueh, Taiwan Shun-ichiro Ohmi, Japan Ephraim Suhir, USA Henry S. H. Chung, Hong Kong Mohamed A. Osman, USA Hannu Tenhunen, Sweden M. Jamal Deen, Canada Ping Feng Pai, Taiwan George S. Tombras, Greece Ahmed El Wakil, UAE Marcelo A. Pavanello, Brazil Spyros Tragoudas, USA Denis Flandre, Belgium Marco Platzner, Germany Chi Kong Tse, Hong Kong P. Franzon, USA Massimo Poncino, Italy Chi-Ying Tsui, Hong Kong Andre Ivanov, Canada Dhiraj K. Pradhan, UK Jan Van der Spiegel, USA Ebroul Izquierdo, UK F. Ren, USA Chin-Long Wey, USA Wen-Ben Jone, USA Communications Sofiene` Affes, Canada K. Giridhar, India Adam Panagos, USA Dharma Agrawal, USA Amoakoh Gyasi-Agyei, Ghana Samuel Pierre, Canada H. Arslan, USA Yaohui Jin, China Nikos C. Sagias, Greece Edward Au, China Mandeep Jit Singh, Malaysia John N. Sahalos, Greece Enzo Baccarelli, Italy Peter Jung, Germany Christian Schlegel, Canada Stefano Basagni, USA Adnan Kavak, Turkey Vinod Sharma, India Guoan Bi, Singapore Rajesh Khanna, India Iickho Song, Korea Jun Bi, China Kiseon Kim, Republic of Korea Ioannis Tomkos, Greece Z. Chen, Singapore D. I. Laurenson, UK Chien Cheng Tseng, Taiwan Rene´ Cumplido, Mexico Tho Le-Ngoc, Canada George Tsoulos, Greece Luca De Nardis, Italy C. Leung, Canada Laura Vanzago, Italy M.-Gabriella Di Benedetto, Italy Petri Mah¨ onen,¨ Germany Roberto Verdone, Italy J. Fiorina, France Mohammad A. Matin, Bangladesh Guosen Yue, USA Lijia Ge, China M. Najar,´ Spain Jian-Kang Zhang, Canada Z. Ghassemlooy, UK M. S. Obaidat, USA Signal Processing S. S. Agaian, USA A. Constantinides, UK Karen O. Egiazarian, Finland Panajotis Agathoklis, Canada Paul Cristea, Romania W. S. Gan, Singapore Jaakko Astola, Finland Petar M. Djuric, USA Z. F. Ghassemlooy, UK Tamal Bose, USA Igor Djurovic,´ Montenegro Ling Guan, Canada Martin Haardt, Germany S. Marshall, UK Srdjan Stankovic, Montenegro Peter Handel, Sweden Antonio Napolitano, Italy Yannis Stylianou, Greece Alfred Hanssen, Norway Sven Nordholm, Australia Ioan Tabus, Finland Andreas Jakobsson, Sweden S. Panchanathan, USA Jarmo Henrik Takala, Finland Jiri Jan, Czech Republic Periasamy K. Rajan, USA A. H. Tewfik, USA S. Jensen, Denmark Cedric´ Richard, France Jitendra Kumar Tugnait, USA Chi Chung Ko, Singapore W. Sandham, UK Vesa Valimaki, Finland M. A. Lagunas, Spain Ravi Sankar, USA Luc Vandendorpe, Belgium J. Lam, Hong Kong Dan Schonfeld, USA Ari J. Visa, Finland D. I. Laurenson, UK Ling Shao, UK JarFerrYang,Taiwan Riccardo Leonardi, Italy John J. Shynk, USA Mark Liao, Taiwan Andreas Spanias, USA Contents ESL Design Methodology, Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, and Zhiru Zhang Volume 2012, Article ID 358281, 2 pages Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing, Yibo Chen, Yu Wang, Yuan Xie, and Andres Takach Volume 2012, Article ID 105250, 14 pages Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections,JasonCong, Karthik Gururaj, Peng Zhang, and Yi Zou Volume 2012, Article ID 691864, 24 pages Selectively Fortifying Reconfigurable Computing Device to Achieve Higher Error Resilience, Mingjie Lin, Yu Bai, and John Wawrzynek Volume 2012, Article ID 593532, 12 pages A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level, Anthony Barreteau, Sebastien´ Le Nours, and Olivier Pasquier Volume 2012, Article ID 537327, 16 pages High-Level Synthesis under Fixed-Point Accuracy Constraint, Daniel Menard, Nicolas Herve, Olivier Sentieys, and Hai-Nam Nguyen Volume 2012, Article ID 906350, 14 pages Automated Generation of Custom Processor Core from C Code, Jelena Trajkovic, Samar Abdi, Gabriela Nicolescu, and Daniel D. Gajski Volume 2012, Article ID 862469, 26 pages Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs, Ghislain Roquier, Endri Bezati, and Marco Mattavelli Volume 2012, Article ID 484962, 11 pages High-Level Synthesis: Productivity, Performance, and Software Constraints, Yun Liang, Kyle Rupnow, Yinan Li, Dongbo Min, Minh N. Do, and Deming Chen Volume 2012, Article ID 649057, 14 pages Hindawi Publishing Corporation Journal of Electrical and Computer Engineering Volume 2012, Article ID 358281, 2 pages doi:10.1155/2012/358281 Editorial ESL Design Methodology Deming Chen,1 Kiyoung Choi,2 Philippe Coussy,3 Yuan Xie, 4 and Zhiru Zhang5 1 Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA 2 School of Electrical Engineering, Seoul National University, Seoul 151-742, Republic of Korea 3 Department of Sciences and Techniques, Lab-STICC, Universit´e de Bretagne-Sud, Lorient 56321, Cedex, France 4 Department of Computer Science and Engineering, Pennsylvania State University at University Park, University Park, PA 16802-1294, USA 5 High-level Synthesis Department, Xilinx Inc., San Jose, CA 95124, USA Correspondence should be addressed to Deming Chen, [email protected] Received 15 May 2012; Accepted 15 May 2012 Copyright © 2012 Deming Chen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. 1. Introduction special issue. These papers cover a wide range of important topics for ESL with rich content and compelling experimen- ESL (electronic system level) design is an emerging design tal results. We introduce the summaries of these papers next. methodology that allows designers to work at higher levels They are categorized into four sections: high-level synthesis, of abstraction than typically supported by register transfer modeling, processor synthesis and hardware/software co- level (RTL) descriptions. Its growth has been driven by the design, and design for error resilience. continuing complexity of IC design, which has made RTL implementation less efficient. 2. High-Level Synthesis ESL methodologies hold the promise of dramatically improving design productivity by accepting designs written In the paper “Parametric yield-driven resource binding in- in high-level languages such as C, System C, C++, and high-level synthesis with multi-Vth/Vdd library and device MATLAB, and so forth, and implementing the function sizing” Y. Chen et al. demonstrated that the increasing impact straight into hardware. Designers can also leverage ESL to of process variability on circuit performance and power optimize performance and power by converting compute requires the employment of statistical approaches in analyses intensive functions into customized cores in System-on-Chip and optimizations at all levels of design abstractions. This (SoC) designs or FPGAs. It can also support early embedded- paper presents a variation-aware high-level synthesis method software development, architectural modeling, and func- that integrates resource sharing with Vth/Vdd selection and tional verification. device sizing to effectively reduce the power consumption ESL has been predicted to grow in both user base and rev- under given timing yield constraint. Experimental results enue steadily in the coming decade. Meanwhile, the design demonstrate significant power yield improvement over con- challenges in ESL remain. Some important research chal- ventional worst-case deterministic techniques. lenges include effective hardware/software partitioning and D. Menard et al. present in the paper “High-level synthesis co-design, high-quality high-level synthesis, seamless system under fixed-point accuracy constraint”anewmethodto IP integration, accurate and fast performance/power model- integrate high level synthesis (HLS) and word-length opti- ing, and efficient debugging and verification, and so forth. misation (WLO). The proposed WLO approach is based on With the invitation of JournalofElectricalandComputer analytical fixed-point analysis to reduce the implementation Engineering of the Hindawi Publishing Corporation, we cost of signal processing applications. Authors demonstrate started the effort of putting together