High Aspect Ratio Silicon Etch - a Review

High Aspect Ratio Silicon EtchHigh Aspect Ratio Silicon Etch - A ReviewBanqiu Wu, Ajay Kumar, Sharma PamarthyApplied Materials974 E Arques Ave, M/S 81505Sunnyvale, CA 94085Abstract High aspect ratio (HAR) silicon etch was thoroughly reviewed, including commonly used terms, history, main applications of the technology, different technological methods, critical challenges, and main theories of the technologies. Chronologically, high aspect ratioHAR silicon etch has been conducted using wet etch in solution, reactive ion etch (RIE) in low density plasma, cryogenicsingle-step etch at cryogenic conditions usingin inductively coupled plasma (ICP) combined with RIE, and time-multiplexed deep silicon etch usingin ICP-RIE configuration reactor, and single-step etch in high density plasma at room or near-room temperature. The Kkey specifications are high aspect ratio, high etch rate, good cross sectionaltrench sidewall profile with smooth surface, low aspect ratio dependent etch (ARDE), and low etch loading effects. Till now, temp-multiplexed etch process is a popular industrial practice, but tThe intrinsic scalloped profile of a time-multiplexed etch process poses a challenge, resulting from alternating between passivation and etch, poses a challenge. Previously, high aspect ratioHAR silicon etch was an application associated primarily with micro-electromechanical systems (MEMS). In recent years, its use in through-silicon-via (TSV) etch applications for three-dimensional (3-D) integrated circuit stacking technology has have spurred research and development of this enabling technology. This potential large scale application requires the high aspect ratioHAR etch with high and stable throughput, controllable profile and surface properties, and low costs. 1. Introduction to HhHigh Aaspect Rratio Ssilicon Eetch High aspect ratio (HAR) silicon etch is also known as deep silicon etch, deep trench silicon etch, silicon deep reactive ion etch (DRIE), and high aspect ratio trench (HART) silicon etch. Page 1 of 51 Since the invention of the integrated circuit (IC) in 1958, silicon etching has been an important technology for the semiconductor industry. Early on, silicon etch meant mainly isotropic wet etch. From the late 1960s, anisotropic silicon etch became an important technology in silicon semiconductor processing.[1] Based on process methods, (HAR) silicon etching can be divided into two categories, i.e. wet etch and plasma etch. Other potential technologies for HAR silicon processing include laser drilling, [2] and ultrasonic drilling. [3] Wet EtchIn the 1960s, silicon etch was found to be orientation-dependent and concentration-dependent in some chemical solutions. [1, 4-58] Silicon used in semiconductors has a single-crystal structure and exhibits different etch rates for individual crystal orientation. When aqueous KOH solution is used for wet etch, etch rates vary for different planes. Etch rates on planes of {111}, {100}, and {110} have been obtained through many studies. [8-12] Silicon etch rates at {111} surface is significantly slower than those on {110} and {100} surfaces atunder a suitable chemical compositions. For example, the etch rate on {110} surface can be several hundred times of the etch rate on {111} surface. By using this etch property, aA rectangular groove with vertical sidewalls and an aspect ratio of several hundred to one can thus be etched on {110} surface withusing a suitable mask. The profile can be vertical and aspect ratios as high as several hundreds can be made. Although this phenomenon is well documented, the underlying mechanism has not been widely explored. ere are many researches and publications on orientation- dependent silicon etching, few publications involved the orientation-dependent silicon etch mechanism. Chrystal surface properties determine the difference in surface density of silicon bonds, bonding energy of silicon atoms, and interstitial space on the interface between silicon and silica. These properties influence oxidation rates on each crystal plane. Both oxidation and etch rates on {111} are slower than surface {110}. The oxidation occurs at the interface between silicon and its oxide, which involves interstitial water molecules in the silica film and silicon at the interface. The high silicon bond density on {111} surface results in a dense oxide in this surface and, therefore, makes the oxidation and etch slower than surface {110} and {100}, but the etch on {110} and {100} can continue owing to the non-denselow density oxide. Silicon etch rate is not a diffusion-limited reaction, but an activation-limited one. When silicon is immersed in ato KOH solution with an oxidizingation agent, silicon oxidation and etch back occur simultaneously. The, determining the visible apparent etch rate resultsing from the difference between the of etch and oxidation reaction Page 2 of 51 rates. This makes the apparent etch rates on different surfaces (e.g. {110, 100, and 111}) significantly different. It as reported that a dense oxide layer was immediately formed on the {111} surface upon immersion in the liquid. [58] prepassive layer was found immediately on {111} surface based on voltage-current curve. Even though orientation-dependent silicon etch can have an very high aspect ratio likeas high as 600, this deep etch technique is inherently limited to the has critical limitation in geometries of structures. For example, it is mainly for fabrication of one-dimensional structures such as deep grooves. This challengefundamentally limits the affects its applications of this technique. [5-8] Another wet process for deep silicon etch is the anodic etching in HF solution, which [explanatory text to come].[9] However, the etch profile does not meet micro-electromechanical systems (MEMS) requirements because [reasons to be inserted here].Plasma EtchPlasma etch is a gas-solid chemical reaction inthat takes place in the presence of a plasma, chamber. Plasma, also known as the forth state of matter, is special gas in which a certain percent of particles are ionized. It an electrically neutral mixture of consists of molecules, atoms, ions, electrons, and photons, but a plasma is electrically neutral.To createFor a stable plasmaenvironment, energy is needed tomust be coupled into the plasma gas phase to sustain the ionization. Electrons are very light particles in plasma. When the same force (e.g., the electric force in an electric field) acts on an electron and a much heaviern ion, the resulting velocityspeed is muchconsiderably different. The result is that the velocityspeed of the elec¬tron will be much higher than that of the heavy ion because of the lower mass. If the collisions are not numerous enough at low-density conditions, i.e., low pressure, the mean kinetic energy or temperature of the electrons will be higher than that of the much heavier ions. In the boundary area of plasma between the bulk plasma and a solid surface, known as the sheath, the properties and charges are different from the plasma’s bulk region, . The main reason ismainly due to the mobility difference between the negative chargeds ( electrons) and the positively chargeds ( ions noted above). The neutral plasma property and fast electron mobility predict accumulation of electrons accumulate near the solid surfacechamsbers area, which results in the existence of a neutral bulk plasma and non-neutral plasma near the wall in, i.e., the sheath. The plasma sheath is a nonneutral potential region between the bulk plasma and a solid surface. In the low-pressure Page 3 of 51 plasma conditions used for HARTSV etching, the mean free path of the electrons is much longer than the sheath thickness, hence the sheath can be treated as a collisionless region.The pPotential drop across the sheath is a function of the relative masses of electrons and ions, electron temperatures, and reactor chamber design. The results is are that the ions have an accelerating voltage across the plasma sheath, enabling an anisotropic plasma etch mechanism. When a DC voltage or a capacitively driven radio frequency voltage is applied onto a surface (cathode), the potential drop across the plasma sheath is enhanced and made adjustable. The potential drop onacross the sheath, approximately equal to also called the (orDC bias,) is one of the most important characteristics of plasma etching. It supplies anisotropic bombardment energy, which significantly reduces the undercut compared with wet etching. This important anisotropyeffect results from the anisotropic energy of supply to the etch surface. The since the reactive, but electrically neutral radicals are not accelerated towards the etch surface by the DC bias. The electrically-charged ions are accelerated towards the etch surface by the DC bias and this ion bombardment creates an anisotropic etch mechanismmay or may not be the bombardment ions. When the reactant is a neutral radical, ion bombardment. Etch and Passivation It is extremely difficult to obtain a good quality HAR silicon trench only relying on anisotropic bombardment supplied by plasma environment. That means passivation on trench sidewall to control lateral etch is a necessary approach, which can be carried out simultaneously with etch in one step or separately in an individual passivation step.One successful process using trench sidewall passivation is cryogenic etch process proposed in 1988. [13] One advantage of cryogenic etch is relatively high selectivity owing to the relative low photoresist (PR) etch rate. Etch rates of 500-1000nm/min were reported with RIE and microwave plasma etching. The etch temperature range was -130 to -100 oC, with pressure of about 10mTorr.[14] To ensure low wafer temperature, liquid nitrogen or helium was placed in direct contact with the wafer, which required with an excellent seal. [14, 15] Cryogenic plasma etch relies on lowering temperatures during plasma treatment to yield less sidewall etching and increasing the dry etch resistance of organic PR masks and hence increases selectivity.[13] To prevent cracking from the low temperature, the photoresist is generally hard-baked before etching.[14] Page 4 of 51 Cryogenic plasma etch was the first practical etch technique for aspect ratios up to 30:1. The technique successfully balances bottom and sidewall etch rates to give the desired sidewall angle. Plasma etch under cryogenic conditions is primarily a chemical reaction. Molecules and atoms absorb plasma energy and dissociate to form ions and very reactive neutral radicals. In a fluorine-based chemical system, the fluorine atom is believed to be the radical responsible for the silicon etch. The cryogenic process uses SF6 and O2 to form a protective, 10-20nm, layer of oxide-fluoride compound (SiOxFy) to suppress on the sidewall etching while simultaneously enhancing the bottom etch rate by ion bombardment.[14] The low temperature reduces erosion of the protective sidewall layer. However, obtaining a straight sidewall for aspect ratios beyond 30:1 is difficult using cryogenic etch.In order to obtain the necessary anisotropy, attempts were made to avoid lateral etching by coating the sidewalls with a polymer film formed from the etch gases. [16] However, ceramic materials were also deposited on the wafer inadvertently by the erosion of the chamber wall around the cathode. [17] This material tended to be deposited only near the aperture of the feature, about 3m from the trench opening, while sidewall protection near the bottom of the feature relied only on the decomposition of carbon-containing chemicals. [17] The resulting trench profile suffered from irregular and rough sidewalls, which were unsatisfactory. For example, when used for MEMS applications, it made mold release difficult and induced unwanted friction in mechanical structures such as axles.Time-multiplexed alternating process is a common method which very successfully uses passivation for HAR silicon etch by alternating sidewall passivation and etch steps. Because of its capability for high aspect ratio feature fabrication, this approach becomes a popular technology in HAR silicon etch. More details about this method will be discussed in the following sections. Simultaneous passivation and etch at room or near room temperature are also applied on single step HAR silicon etch process using chemicals similar with those used in cryogenic process. It is challenge to control this passivation and keep balance between lateral and vertical etch rates. supplies only energy.Microelectromechanical systemsThe basic requirement for deep silicon etch is high etch rate (3 m/min), high aspect ratio (30 or higher), and high etch rate selectivity (100).[10] These numbers briefly give us an outline for identifying the process capability in late 1990s.Page 5 of 51 For MEMS and through-silicon-via (TSV) etch applications, the etch required trench depth has a wide ranges, from a few micrometers to several hundred micrometers, which is much deeper than those for found in IC wafer processing.[1114, 1218] Deep silicon etch is relatively “deep” compared with the layers etched on IC wafers. DemandThe requirement forfor a deep silicon etch in a for silicon diode array target fabrication was reported in the early 1970s.[13, 14] From the mid-1990s, plasma deep silicon etch was used for capacitors and isolation.[15-18] This early deep silicon etch was for making deep holes and trenches in silicon substrates to enhance charge storage in dynamic random access memories (DRAM),[19-21] as well asand for high aspect ratioHAR -Si gate etch.[22] This category of silicon etch is also known as deep silicon etch, deep trench silicon etch, deep reactive ion etch (DRIE), high aspect ratio trench (HART) etch, and high aspect ratioHAR silicon etch. Competing technologies are laser drilling, [23] ultrasonic drilling, [24] and wet etching.[25] For TSV applications, DRIE using an ICP plasma source (ICP-DRIE) is believed the most common techniqueto be the number one candidate.[26] In the 1980s, many studies were performed to explore the use of deep silicon etch for MEMS micromachining,.[13, 17, 19] and Large-scale application of deep silicon etch volume manufacturingfor this application began in the 1990s. Before the mid-1990s, etch for both semiconductor films and micromachining was mainly limited for to films, such as films on wafers for semiconductor devices and films for micromachining, both of were typically onlyup to a few micrometers in thickness. Micromachining In MEMS, thison these films is known as “surface” micromachining. In the early 1990s, bBulk micromachined devicesMEMS development spurred research and developmentinto of plasma etch deep into the bulk silicon, i.e. deep silicon etch, to enable the fabrication of. These devices included piezoresistive pressure and acceleration sensors, microvalves and micropumps, and implantable neural probes and stimulators.[2720] RIE was used to etch depths of 100 to 600 m. At that time, the basic requirements for deep silicon etch iswere high etch rate (3 m/min), high aspect ratio (30 or higher), and high etch rate selectivity between silicon and the mask material such as photoresist (100).[21] These numbers briefly give us an outline for identifying the process capability.The history of deep silicon etch dates back to the 1980s.[28-30] The challenge was the necessary anisotropy. Early on, attempts were made to were made to prevent lateral etching by using coating the sidewalls with a polymer film formed from the etch gases. [31] and materials released from the cathode plate. [28] The issue was that the ceramic materials were also releaseddeposited on the wafer inadvertently by the erosion of the from the chamber Page 6 of 51 wall around the cathode. [26] This material tended to bewere deposited only near the aperture of the feature, but did not attach to the bottom of features deeper than about 3 m from the opening. whileThe sidewall protection near the bottom of the feature reliedied only on the decomposition of carbon-containing chemicals from the etchant gases. [28] The resulting The profile suffered from irregular and rough sidewalls, which were un of this method, therefore, was not satisfactory for MEMS applications because it made mold release difficult and induced unwanted friction in mechanical structures such as axles.for high aspect ratio trench. This Although silicon deep trench etch was proposed early, the etch technology did not make significant progress until the mid-1990s whenIintensive MEMS development resulted in significant progress being made in silicon deep trench etch in the mid-1990s. received intensive attentionsA and applications proliferated, including silicon molds,[3222, 3323] silicon pillars,[3424] ridges, optical gratings,[3525-327] attenuators,[3828] Fresnel lenses,[3929] silicon nanopillar arrays (Ffigure 5) for biotechnology applications, [4030] micro turbines, [4131, 4232] accelerometers, [4333, 4434] acoustic filters, [4535] and gyroscopes,[4636, 4737] as well as CMOS- (complementary metal-oxide-semiconductor) based microphones (late 1990s). For more information on sSecondary effects and issues in high aspect ratioHAR etch for MEMS applications, see references were investigated. [4838-5401]. The development of TSV structures, where two or more chips are joined by vertical interconnects running through the stack has resulted in fFurther intensive studies of into deep silicon etch are related to its application in TSV etch. [51] In TSV, two or more vertically stacked chips are joined by vertical interconnects running through the stack (i.e., across the interface between two or more adjacent chips) and functioning as components of the integrated circuit. TSV etch makes the via holes by which the vertically stacked chips are connected. Although etching completely through the substrate is not required because Although a thinning step is used during the packaging process, an etch depth of more than 100 m is necessary for this application. For cost reasonsGiven the demands for containing costs of volume production, TSV etch also requires high etch rate and to enable high throughput, as well as and smooth sidewalls to ensure the optimal fill of conducting materials in subsequent processint. These requirements make deep silicon etch for TSV very challenging.Page 7 of 51 Cryogenic EtchA A cryogenic process for TSV etch was for high aspect ratio etch was proposed in 1988. [29] In the 1990s, this process was intensively studied. One advantage of cryogenic etch is high, typically over 30, selectivity owing to the relative low photoresist (PR) etch rate (e.g., selectivity of 30). Etch rates of 500- to 1000 nm/min were reported withRIE and microwave plasma etching. The etch temperature range was -130 to -100oC or even lower, with pressure of about 10 mTorr.[11] The low wafer temperature was obtained by using liquid nitrogen cooling, or helium was placed in fluid, which directly contacted with the wafer, which required with an excellent seal. [11, 52] Cryogenic plasma etch relies on lower temperatures during plasma treatment to yield less sidewall etching and increase the dry etch resistance of organic PR masks and hence increase selectivity.[29] HoweverT, the low temperature may cause photoresist layer cracking, so the photoresist used needs to be hard-baked to prevent cracking from the low temperature, the photoresist must be hard-baked before etching and increase the etch resistance.[11] Cryogenic plasma etch was the first practical etch technique for aspect ratios up to 30:1. The technique successfully balances bottom and sidewall etch rates to give the desired sidewall angle. Both undercryogenic and RIE etches are primarily a plasma-enhanced chemical reactions. In plasma environments, plasma energy is absorbed by molecules and atoms, anddissociateing these particles to form very reactive electric-neutral radicals. In a fluorine-based chemical system, the fluorine atom is believed to be the radical responsible for the silicon etch. The cryogenic process uses SF6 and O2 to form a protective, 10-20nm, layer of oxide-fluoride compound (SiOxFy) to suppress on the sidewall etchings (about 10-20nm thick) while simultaneously enhancing the bottom etch rate by ion bombardment ion bombardment.[11] The low temperature reduces erosion of the protective sidewall layer. The strategy of balancing sidewall and trench bottom etch rates was realized by forming isotropic passivation layer deposition and anisotropically etching the bottom part of the layer. Thus, only the bottom is etched while the sidewall remains protected. However, the challenge is obtaining a straight sidewall for aspect ratios beyond 30:1 is difficult using cryogenic etch.Through-Silicon ViasThe development of TSV structures, where two or more chips are joined by vertical interconnects running through the stack has resulted in further intensive studies into deep silicon etch. [42] TSV etch makes the via holes Page 8 of 51 for connecting the vertically stacked chips. Although etching completely through the substrate is not required because a thinning step is used during the packaging process, an etch depth of more than 100m is necessary. For cost reasons, TSV etch requires high etch rate to enable high throughput, and smooth sidewalls to ensure the optimal fill of conducting materials in subsequent processing. These requirements make deep silicon etch for TSV very challenging.In 1996, an US patent disclosed a polymer passivation and etch method that used a time-multiplexed etch process alternating etch and passivation steps, i.e., the Bosch process. [53] Owing to the time-multiplexed process, a much higher aspect ratio was obtained with significantly high etch selectivity. Since this method was first proposed, many modified versions have been studied. [54-58] Obviously, Time-multiplexed deep silicon etch uses a repetitive cycle of polymer passivation and etch, but the passivation is not limited to polymer deposition and o. Oxygen and hydrogen have been reported for passivationthis purpose. [59, 60] The deep vertical etching process includes sequential oxygen passivation and SF6 etching at low density plasma of 0.25-0.5 W/cm2. Pressures were 100 mTorr and 350 mTorr for etch and passivation, respectively. Features were more than 15 m deep and between 100 to 600 nm wide. The main application has been for MOSFET transistor fabrication.[59] The use of through-silicon vias (TSVs) etch for stacked-chip applications has a large potential market. It was estimated that 3-D integration packaging was is equivalent to two generations of to the lateral feature size shrinking by two generations.[6143] When TSV etch occurs before wafer the fabrication of active circuit features such as transistors, the process is called “Viavia-first.” Conversely, it is called “via-last” if the TSV is etched after the wafer active features are completehas been processed. Obviously, the via-last process will etch through not only silicon, but also all the top layers deposited during prior wafer processing. After the via is etched, the hole is typically lined with a dielectric “sleeve” (e.g. SiO2), deposited by CVD, and then filled with electroplated copper or tungsten. [6244] The first high volume application of TSVs was has recently been used in the industrial production of CMOS image sensors using a via-last approach. After fabrication of the sensor array, the wafer is thinned using a grinding process, inverted bonded to a by bonding active silicon onto glass carrier. The and creating contacts are then formed from the backside. TSVs are; it is predicted to be in use for stacked chips by 2010.[6345] Page 9 of 51 TSVs typically are large features, with diameters 1-50μm and depths up to 150μm with aspect ratios fromup to 1-15:1 depending on the application and integration scheme.HAR SFinFETsmall Features for IC FabricationsThe requirement for a deep silicon etch for silicon diode array fabrication was reported in the early 1970s.[46, 47] Later, plasma deep silicon etch was used for capacitors and isolation.[48-51] This early deep silicon etch was for making deep holes and trenches in silicon substrates to enhance charge storage in DRAM,[52-54] and for HAR -Si gate etch.[55]In 2006, a very small feature with high aspect ratio (11 nm wide and 87 nm high) was etched on to form a silicon fin for a FinFET device.[6456] This extremely small feature high aspect ratioHAR silicon etch shows the potential applications in this promising technology. Other example is for fabrication of shallow trench isolation (STI) features between MOSFET transistors or DRAM cells which can bewith features of more than 15 m deep and 100 - 600 nm wide.[57]Challenges of HAR Silicon EtchThe success of high aspect ratioHAR silicon etch depends on controlling the lateral etch rate and enhancing the vertical etch rate. Controlling the etch rates in these two directions relies on the ion incidence angle distribution and the dependence of the silicon and passivation layer, etch rates upon dependence on the ion angle, and passivation layer etch rate dependence on the ion angle. Ideally,More accurately speaking, high aspect ratio plasma etch should occur in a process window wherethe vertical bombardment energy is should be high enough to assist achieve the desiredthe moderate vertical etch rate, but while the lateral bombardment component is should not be strong enough to significantly etch through the passivation layer and allow lateral etching to silicon. The key challenges of deep silicon etch areto achieve high aspect ratio with, smooth, usually vertical, sidewall profiles, and surface roughness are to obtain high etch rate and selectivity, and control loading effects, aspect ratio dependent etching (, ARDE), bottling, micrograss, tilting, and notchingselectivity, etch rate, microloading, and macroloading. Each of these aspects will be discussed in the following sections.Page 10 of 51 2. Time-multiplexed alternating process The tStrategies for obtaining high aspect ratio silicon etch have been well known since the 1980s, i.e., toby controlling the vertical and lateral etch rates by using surface modification, such as oxidation and polymer coating. The key challenge is how to createing a stable and controllable process for practical uses.TIn 1996, a time-multiplexed alternating process for HAR silicon etch, which of alternatesing etching and polymerization steps, was invented by Laemer and Schilp. The, patent was assigned to Robert Bosch GmbH in 1996,. [53] so This it is also known as the Bosch method for high aspect ratio silicon etch. [58] The time- multiplexed process allowed a much higher aspect ratio to be obtained with very high etch selectivity. Since this method was first proposed, many modified versions have been studied. [5459-5863] The original etch gas was SF6 and polymerization gases were CHF3 and Ar. Other etch gases included NF3 and CF4. The passivation mechanism is not limited to polymer deposition; oxygen and hydrogen have been reported for this purpose. [5957, 6064] TThus far, the time-multiplexed etch process has proven popular for high aspect ratio trenches in MEMS and TSV applications.EachThe first step is the polymerization step is by CHF3, followed by the an etch step, which rapidly removes the polymer layer on the bottom of the feature while partially removinges the polymer layer on the sidewall . The polymers on the bottom are rapidly broken through during the subsequent etch step. The process is shown in (Figure1). [65] The partial polymer removal To protects the sidewall, polymers on the sidewall should not be removed completely. EThe etch steps and the polymerpassivation steps are alternated until the predetermined desired etch depth on silicon is reached. The polymer is Teflon-like and approximately 50 nm is deposited thick on the sidewall and base. Although etch and polymerization is are performed alternately, there is a gas flow overlap owing due to the gas residence time distributions in the etch chamber. This phenomena makes it possible to operate the time- multiplexed method with continuous flows of SF6 and C4F8 by suppressing reducing the time durations inof each step.[66] The Ccontinuous gas flow reduces the sidewall s of gases have superior properties for improving the “scallop”ing profiles that tend to form as a result of the alternating etch and passivation steps. <Figure 1 here>Page 11 of 51 A Ttypical etch condition of the original time-multiplexed etch process typically used is: SF6 gas flow rate of up to 100 sccm, a chamber pressure of 10- to 10mTorr0 bar, microwave power for plasma generation of 300- to 1200W watts and 3- to 5 W bias power applied to the cathode. Later, C4F8 replaced CHF3 as a passivation gas for better passivation performance and ICP was widely used instead of microwave plasma.For the time-multiplexed process, the balance of etch and passivation is critical to achieving anisotropic etch and process stability, process window selection and stability controland. Thise matching between polymerization and etching can be adjusted by both either the etch and or the polymerization process. For a fixed etch processstep, the overall etch rate is a function of the polymer processstep, depending on C4F8 flow rate and polymerization step, or pulsing, time (, as shown in Figure 2). [1021] It can be seen in Figure 2(a) that the overall etch rate drops with an increase in C4F8 flow rate, but at above the optimal condition (circled), the etch rate drops sharply, i.e., the optimum flow rate is where the maximum anisotropic etch rate with stable polymerization is achieved. When the C4F8 flow rate is higher than the optimal condition, the etch pulse is not long enough to penetrate the bottom polymer. Below the optimal condition, the sidewall polymer is also completely etched through and isotropic etch results. Two regions on the plot of C4F8 flow rate versus pulse frequency inverse of passivation time are identified (Figure 2b). These two regions are the polymer deposition region and isotropic region, as shown in Figure 2(b). Along tThe process window in this narrow area along the dividing line between these two regions, has an anisotropic etch propertyis achieved. The narrowness of this region process widow means difficult control of process stability is difficult to achieve for the time-multiplexed etch process, i.e., the “process window” is narrow..<Figure 2 here>Polymerization rate and polymer etch resistance are important parameters because both of themthey influence the overall etch rate and profile. However, polymers are not a single stoichiometric compound, but a mixing mixture of some organic chemicals. It was reported that two polymer film composition regimes were found, one of which has a high fluorine-to-carbon ratio (F/C = 1.6) at occurs at low pressure and high RF power process widows. The other one regime has a low ratio (F/C = 1.2) at atprocess conditions with high pressure and low RF power process conditions. [67] Optical emission spectroscopy (OES) results (Ffigure 3) indicate a high content of C3, C2, and F in the plasma that which the corresponds to a high F/C ratio in the deposited film [67]corresponds a high content of C3,Page 12 of 51 C2, and F in plasma, while a low F/C ratio in film (poor CF2) corresponds a high content of CF2 in plasma.[67] This means that CF2-rich plasma produces CF2-poor film. This phenomenon indicates that the polymerization process is not controlled by a concentration factor, but by an activation factor that is enhanced by high plasma power and low pressure. The optimal F/C ratio for this study is 1.45 to give the best balance between deposition rate and etch resistance. OES results are shown in Figure 3.[67] <Figure 3 here>Polymer etch resistance is critical to overall etch rate and selectivity. It was found that a low F/C ratio film is more etch resistant than those one with a high ratios.[67] However, the etch-rate-to-deposition -rate of a low F/C film is undesirably high during the deposition step. A low etch-to-deposition rate in the deposition step is preferred during process optimization even though it corresponds to a low etch resistance in the etch step to maximize the overall etch rate.The main advantages of the time-multiplexed etch process are the controllable and, stable profile; high etch selectivity; high etch rate; and high aspect ratio. Disadvantages include the scallop-shape profile resulting from the alternating etch and polymerization processes, and micrograss. Etch rate in the time-multiplexed etch process is very sensitive to feature sizes, increasing with an increase in feature dimensions. This property tends to produce negative profiles on large open areas.[11] In 1999, a maximum etch rate of 10 m/min was obtained, while a better profile corresponded with a 6 m/min etch rate. The etch was achieved at room temperature with the etch rate increasing from center to edge by 10-15% in the ICP-RIE reactor. [68] Later, an etch rate in excess of 20 m/min become practical.[69] A regular time-multiplexed etch process produces a high sidewall ripple of 100-200 nm. Reducing etch and passivation time reduces the sidewall ripple to about 10 nm at the expense of sidewall profile angle.[70] Post-etch wet processing using KOH and IPA can reduce the sidewall roughness down to 6 nm, but the process is a little too complicated.[70] Table 1 shows a range of published time-multiplexed silicon etch process conditions and results. The table indicates a variety of process windowsconditions which exhibit ,a but the reasonable balance ofcontrolling of etch and deposition extents ratesshould be kept. Page 13 of 51 Table 1. Comparison of time-multiplexed ICP-RIE etch processesPassivation step Etch step Rate Process Pressure Flow rate Source Bias Time Pressure Flow rate Source Bias Time Gas Gas m/s mTorr sccm W W s mTorr sccm W W s BoschCHF3 SF6 300- Ref. 7.5-75 < 100 300-1200 0 -- 7.5-75 < 100 3-5 -- 2-20 Ar Ar 1200 [5358]Ref. [66] -- C4F8 90 -- 2 -- -- SF6 136 -- 12 -- 3.3Ref. SF6 26017 C4F8 120 1000 0 5 40 2800 16 6.5 --[7168] O2 26 Ref.20 C4F8 40 600 0 30 20 SF6 40 600 -70 V 60 -- [5459]* Ref.17 C4F8 85 600 0 5 26 SF6 130 600 20 6 3.0-3.5 [7269] Ref.-- C4F8 80 600 0 9 -- SF6 130 600 15 11 2.5-3.0 [7370] Ref.-- C4F8 200 1500 0 1 -- SF6 250 1500 80** 3 -- [7471]SF6 130Ref. [65] -- C4F8 100 600 0 6 -- 600 12 7 --O2 13Ref. SF6 12510 C4F8 95 625 0 5 20 650 11 5 1.25[7572] O2 7Ref. C4F8 or50 20 200 -50 V -- 5 SF6 5 200 -100 V -- --[7673] C4F6SF6 30 Ref.20 C4F8 85 600 0 5 20 O2 5 600 600 7 -- [7774] Ar ArC4F8 70Ref. SF6 100 22 Ar 40 850 0 5 24 850 8 7 -- [7875] Ar 40SF6 1 Ref.[7976]** 50 C4F8 10 200 -50 V 120 5 SF6 4 200 -200 V 120 --* Ref.-- C4F8 80 600 0 9 -- SF6 130 600 15 11 2.5-3.1 [7370] * Modified Bosch process with a transition step added (at temperature of -5oC).** 260 kHz low frequency, 10 ms on, 90 ms off*** Faraday cage, placed between the wafer and the plasma source, was used for this recipe to improve selectivityPage 14 of 51 In deep silicon etch with an ICP-RIE configuration, Pprocess performance is affected by many parameters among which gas flow rate, pressure, and applied RF powers are the most critical. [66] When As pressure increases, the concentrations of atomic fluorine and other radicals increase, resulting in a higher etch rate. However, high pressure reduces ion energy, sheath width, and DC bias drop across the plasma sheath, which and then enhancestends to result in the isotropic profiles. [66] Conversely, higher bias power will increase the DC self-bias and ion directionality, and thenwhich promotes anisotropy. However, increasing bBias power or ion bombardment energy increases the photoresist etch rate faster than the silicon etch rate, leading to lower etch selectivity. After the etch process is complete, tThe passivation film created in the time-multiplexed etch process can be removed by plasma ashing or by immersion in using ethoxy-nonafluorobutane (C4F9OC2H5), which is commercially available as 3M Novec Engineered Fluids HFE-7200. [7370] C4F6 was investigated as an alternative gas for passivation. [7673] When C4F8 is used, there was a significant measurable silicon etch rate in the passivation step atunder certain some process windowsconditions, but no silicon etch rate was observed when C4F6 was used. The reason was that the low F/C ratio of the fluorocarbon film tended to slow the etch rate of the film. [7673, 8077, 8178] The polymer deposition rates in C4F8 and C4F6 plasmas are also different (are shown in Figure 4). [8279] Due to the difference in polymer propertiesy difference resulting from use of C4F6, the process parameters should be adjusted from the C4F8 process window to obtain a requiredthe desired profile. Under the experimental conditions, the anisotropy of the silicon trench using C4F6 passivation gas was found to be comparable to or better than that with C4F8 passivation gas. [7673] It was reported that sub-40nm silicon pillar arrays fabricated using time-multiplexed deep silicon etch achieved sub-40 nm dimension feature with 1.5 m depth, an (aspect ratio of 50:1, or even 60:1), for fabrication of silicon pillar arrays, as shown in (Figure 5).[7774] <Figure 4 here><Figure 5 here>Etch rate and selectivity Silicon eEtch rate increases with pressure in the low pressure region due to the increases in atomic fluorine concentration. However, increasing pressure further pressure increase results in an etch rate decrease owing becauseto the ion energy and or radical flux decrease in high pressure plasma.[66] Thus, tThere is a particular Page 15 of 51 pressure at which maximum value on the etch rate is observed versus pressure curve plotting. The silicon etch rate is almost independent of the C4F8 flow rate and RIE power during passivation. [66] GeometricallyO, overall etch rate is dependent on aspect ratio, rather than trench depth.[1211] It decreases with an increase in aspect ratio.[1118]. Etch rate in the time-multiplexed etch process is very sensitive to feature sizes, increasing with an increase in feature dimensions. This property, aspect-ratio dependent etching (ARDE), further explored below, tends to produce negative profiles on large open areas.[14] Increasing cathode temperature also results inincreases high etch rate.[7269] However, the increase in temperature may cause more undercut. hHigher temperature also causes higher sidewall etch rate as well asand lower polymer deposition rate, leading to sidewall erosion and undercut profiles. [2641] Adding argon helps increase ion bombardment, which increase the etch rate and anisotropy, thus and improvinge sidewall profile.[7269] The chemical reaction fundamentals determine that, overall, silicon etch rate increases with plasma power by enhancing, to increase dissociation in the plasma and SF6 flow rate by raisingto increase the concentration of reactants at the wafer surface. However, many responses have to be considered when selecting the values of these parameters can affect etch characteristics such as sidewall profile and selectivity, so other parameters will probably have to be modified to compensate.The effect of the Etch rate changes with total silicon area exposed to the plasma (loading) on etch rate were explained by the rate equation proposed by Mogab. [8380] Silicon etch is a chemical reaction in a plasma environment. The greater the etch surface area, the lower the etch rate for the same features at the same kinetic conditions. [8380] In 1999, a maximum etch rate of 10 m/min was obtained, while adjusting process conditions to improve the better profile correspondedreduced the etch rate to with a 6 m/min etch rate. The etchThis result was achieved at room temperature with the etch rate increasing from center to edge by 10-15% in the ICP-RIE reactor. [81] Later, an etch rate in excess of 20 m/min becaome practical. [82] Etch Rate UniformityBesides Eetch rate, its uniformity is also a critical responseparameter. All parameters factors affecting etch rate can cause etch rate non-uniformity, including plasma power, gas flow, temperature, and pressure distribution. Page 16 of 51 Plasma density is higher at points closer to the RF power coils, resulting in an increase in local etch rate. Therefore, the etch rate uniformity is strongly affected by the etch tool design. Process changes Spatial variation of etch rate can occur at different scales of domain. Etch rate non-uniformity can be viewed in terms of an area in the die and of the entire wafer. The non-uniformity in a die is a kind of microloading effect, but the one or across the wafer is influenced by many parameters, such as process windows and hardware design. To improve etch rate uniformity, sometimes process optimization is at the expense of the average magnitude of etch rate, such as by increasing the flow rate of the C4F8 passivation gas, decreasing the SF6 flow rate, and cooling the wafer to a temperature of about 5oC may improve etch rate uniformity, but at the expense of reduction of e the overall etch rate.[1218] Etch rate uniformity deteriorates when pressure or average loading increase. Empirically, it has been found that etch rate uniformity, while it may improves when a small amount of oxygen is present in etch step. [1218] According to the fundamental kinetics fundamentals, etch rate uniformity on a wafer is affected by temperature uniformity. Etch rate sensitivity to temperature is dependent on the etch reaction activation energy. The higher the activation energy, the more influence the temperature has. Because silicon etch reaction is a highly exothermic reaction (-176 kcal/mol Si), heat release and its effects on etch uniformity should be considered. However, no systematic studies were found that related etch rate uniformity effects to wafer temperature distributions. Another parameter affecting etch rate uniformity is the local concentration of the reaction radical, i.e., the atomic fluorine. Etch rate is not only dependent on the gas flow pattern, but also on the local consumption rate and transport phenomena. The flow pattern plays an more important role in determining the macro scale etch rate pattern distribution, while the mass transfer in the plasma sheath and in the trench determine the local reaction rate. The former flow pattern generally is not affected by the extent desiredof the etch reactiondepth, but the latter local reaction rate depends on the trench depth or aspect ratio. In other words, the etch trench depth uniformity is a function of etch depth and feature dimension. Ideally, There are two strategies for obtaining an overall uniform etch trench depth,. One is to have the a uniform instant etch rate through the whole etch period would be achieved. In practice, this is not necessary, because it is the final, or time-averaged, etch rate uniformity that is important. Instead, a small number of process steps with Another option is to use constant process parameters can be used or recipes. Each step, which does not have instant etch rate uniformity, but in combination, have an good overall (final) etch depth uniformity is achieved or time-Page 17 of 51 averaged etch rate uniformity. For example, a fast etch rate step with a certain uniformity signature may be combined with a slower step with the opposite signature to give good overall etch depth uniformity.Hardware design, such as ICP coils and cathode, plays an important role in final etch trench depth uniformity. It was reported that etch rate uniformity could be improved by cooling the material being etched, putting the etching into an ion-activated reaction-rate-limited regime, where the ion energy, not the local concentration of reactants, dominates the etch rate.[8483] However, other researchers have found that iEtch rate uniformity is also sensitive to process window and parameters. Increases in SF6 flow or RF power, or decreases in chamber pressure tend to improve etch rate uniformity.[8584] Of course, hardware design plays an important role in final etch trench depth uniformity. If the hardware is not uniform, no amount of process tuning can produce a satisfactory result. The cathode must have uniform temperature distribution and the ICP source must produce a uniform ion density across the wafer.SelectivityAnother important etch rate parameter is the relative silicon etch rate with respect to resist mask (typically PR) etch rate, i.e., the etch selectivity. If the PR is fully depleted before the end of the etch process, the top surface of the substrate will be damaged. The photoresist PR etch rate increases significantly when high RIE, or bias, power is applied to the cathode. Therefore, the bias power, which is related to or bombardment strength, is the important parameter for selectivity determination. That etch rate increases with bias power is well known, but an high increase in bias power tends to increaseis limited PR erosion, so b PR thickness becomes the limiting factory photoresist thickness. Recently, new PR materials formulated for ultra-thick photoresist (12 to 100 m) applications was reported.[8685] It is expected that the new ultra-thick resistPR (SIPR-7126 by Shin-Etsu) will be helpful in enhancing etch rate by allowing higher bias power to be used changing process windows.Profile A straight and smooth profile is generally required for high aspect ratio silicon etchHAR silicon etch, but for some silicon mold fabrication and TSV applications, a sloped sidewall angle (e.g.of around 85°) is preferred. One Page 18 of 51 common profile issue is Tthe characteristic scalloped shape resulting from the time-multiplexed process can be problematic for downstream processing, so profile control is critical.The shape of the sScallopsed profile is determined by many process parameters. When the process is well controlled, the peak-to-peak valley value distance on scallop profile can beis in the range of 50 nm.[66] It was reported that the ratio of power to pressure had a significant influence on the scallop shape, with a higher ratio tending to have produce a smoother profile.[66] Sidewall profile depends on parameters in the passivation and etch steps and sidewall slope is dependent on the ratio of the etching and /passivatingpassivation step times. The A relatively long etch cycle compared with passivation tends to give a reentrant profile. Similarly, too short an etch time results in a positive slope.[. [8786] When a regular time-multiplexed etch process is used, tThe etch and passivatingpassivation cycles are quite often maintained for only a few seconds (e.g. 3-5 seconds) to suppress sidewall scalloping. Owing to the residence time, the short cycle time results in some overlap of the gases with consequent mixing during the step transition. It was believed that this gas mixing in the plasma environment promoted the polymerization.[8887] However, this mixing of gases may make it difficult to control the profile angle by using varying the etching and /passivatingpassivation time periodss. . Therefore, a third step was sometimes introduced to completely evacuate the reactant gases between steps.[5459] In some applications, such as of mold formation, a sloped silicon sidewall, e.g., 85 degrees, is desired for good mold release.[54] Adding a third step made the creation of sloped sidewalls foris mold release simple process control easy. Etch profile tends to changes with trench depth or aspect ratio. A practical strategy to solve this problem is create a multi-step process recipe to change the bias power or DC bias voltage according to the depth. It was reported that bias voltage during etch steps was varied from -70 V for 0-20 m etching, -80 V for 20-30 m etching, and to -90 V for 30-40 m etching to achieve a vertical profile.[5459] The variation of voltages with etch step time can improve the overall profile, but there may be noticeable transition part of ain the profile between the different steps. Adding mMore steps or continuously changinge of bias voltage with time are preferredcan be used to obtain a straight smoother profile.Profile angle and sidewall surface roughness are very important for most applications. When high aspect ratioHAR silicon etch is used for silicon mold fabrication, a wavy profile could can make demolding difficult. A post-passivation step using C4F8 was reported to be effective for reducing the root mean square (RMS) sidewall Page 19 of 51 roughness of the silicon master mold trenches by about half and thus reducing the friction coefficient of the silicon surface six-fold.[3323] The A wavy scalloped profile can also cause problems for the subsequent metal fill in TSV applications. It To achieverequires the least scalloped profile possible, so that some applications use a wet etch has been used to smooth the surface after dry etch.[7088] Post-etch wet processing using KOH and IPA can reduce the sidewall roughness down to 6 nm, but the process is a little too complicated.[84] Adding oxygen in etch step may also result in a smoother surface but can a lower etch selectivity.[7269] A regularconventional time-multiplexed etch process produces a high sidewall ripple of 100-200 nm. ProcessO optimization such as controllingof etch and passivation time reduces the sidewall ripple to about 10 nm at the expense of sidewall profile angle.[88, 89] Because the etch rate reduces as the depth increases (because of ARDE, described below)Owing to the etch rate dependency on aspect ratio, the scallops on the upper part of theed trench sidewalls are deeper and further apart than lower down, i.e. the surface roughness decreases with depthon top of the trench is higher than that at the lower position. Therefore, TSV is sometimes etched by a steady-state one step recipe for the first part and then by a time- multiplexed recipe to etch the followingto the final depth part in order to reduce the trench sidewall roughness. However, the trenches makemade by this method hasshow a clear connectingtransition between the two process regimes line.To date, scalloping asperity of 10 nm was reported.[89] TFor TSV application, there are several critical challenges for the development and adoption of 3-D integration technologies. One of them is the formation of a reliable through-silicon interconnectionTSVs. Creating HAR TSVs is more challenging because it there is normally insufficient space between features to accommodate a tapered sidewall The foremost challenge is to form tapered or sloped via sidewalls while still maintaining the required aspect ratio.[1346] Because the intrinsic scalloped profile may cause intermittent barrier and seed layer coverage leading to inter-via electrical leakage current,[90] the addition of tapered profiles with a smoothing isotropic dry etch process after the time-multiplexed trench etch wasby an isotropic dry etch were studied.[7269] The main purpose of the isotropic etch was to help to smooth the scallops and tapering the via profile and thus to prevent void formation during the copper electroplating process. Via tapering helps conformal deposition of isolation dielectric, copper diffusion barrier metallization, and copper seed metallization over the sidewalls of the deep silicon viaTSV, and .[7269, 91] Commonly, vias for TSV are approximately 150-200 m deep with a V-shaped cross section to Page 20 of 51 facilitatebulk metal filling processes, such as electroplating.[7269] Recent progress in thin wafer manufacturing and handling capability allow shallower vias depths to be used (50-100 µm).Process conditions for theThe isotropic etch condition for tapering profile isotropic etch was were reported to be: pressure of 12 mTorr pressure, 180sccm SF6 flow rate of 180 sccm, 18sccm O2 flow rate of 18 sccm, 700W ICP power, 20W of 700 watts, RIE power of 20 watts, and process time of 10 minutes.[7269] From This process is not truly isotropic as wet processbecause the lateral etch rate is higher at the top of the trench than lower down, but the result is a smooth tapered profilethis condition, the final etch profile was not a real “isotropic,” but only “imperfect” anisotropy.[7269, 91] Whether or not to use a tapered profile is mainly dependent on the bulk conductor fill processing. Usually, metallization for filling the via employs CVD tungsten or electroplated copper; for these, tapered profiles are preferred because they allow higher fill rates than non-tapered TSVs.[92] Due to the effect importance of surface roughness on in the MEMS and TSV applications, sidewall smoothness has received much attention and investigation. The side wall ripple results mainly from the isotropic etch in a time- multiplexed process. Therefore, process parameters eliminating the isotropic property are helpful in smoothing the sidewall surface. Anisotropic etch with high bias power in the etch step can help to minimize the sidewall ripple, but it will decrease the selectivity.[93] To solve this problem, using a Faraday cage above the cathode for high bias power in the etch step was tested,.[7976, 94] The Faraday cage has a grid above the cathode, resulting in a lower ion-to-radical ratio. [76, 94] With this configuration, sidewall roughness was improved without significant decrease in selectivity. The method has not been widely accepted for production becausefor of the Faraday cage above the wafer may introduce defectivity issues associated with the presence of the Faraday cage above the wafer.Another common method for controlling sidewall smoothness is to reduce the etch and polymerization step times, but the suitable ratio of the etch and deposition times should be kept to ensure the vertical sidewall profile. Due to the change in etch performance changes with aspect ratio, continuous control and adjustment of etch parameters as the etch progresses is a suitable strategy.[95] Profile tilting, where the etch does not proceed normal to the wafer surface, is a special profile issue, caused by “boundary distortion” or local differences in radical density and ion bombardment angle, typically at the edge of the wafer.[96] Increasing the sheath thickness by using lower process pressure, can improve tilting. Page 21 of 51 Therefore, low pressure tends to improve or eliminate tilting. Profile angle changes with feature size are also an issue. If the process is optimized to give aFor a fixed process, vertical profile was obtained on a certain critical feature size, here called critical feature size. F features larger than critical feature size may have a reentrant profile, while ones smaller than critical feature size will have positive profile angle. The phenomenon may be reduced by changing process parameters such as chamber pressure.Aspect Ratio Dependent EtchRDE ARDE, also loosely referred as to RIE lag, exists in all etch processes, but is of particular especially concern when fabricatingin HAR structures high aspect ratio etch. In high aspect ratioHAR etch applications in MEMS or TSV 3-D stacking, features with a wide variation of different sizes on one wafer have to be etched simultaneously. Also, an ideal process would tolerate different batches of same-sized features from (wafer to wafer) without modification have to be dealt with. For TSV etch, via dimensions for the via-first process are about 1- to 20 m with aspect ratios of 3:1 to - to 10:1, while via dimensions for the via-last process are about 20 to 50 m with aspect ratios of 3:1 to - to 15:1.[6345] This variance wide range indicates the difficulty of etching these features in one process condition.ARDE has been a challenge for micromachining and TSV applications. For some applications, etch rate differences may cause a process control problem. Taking TSV silicon etch as example, features of different sizes co- exist on one wafer.In MEMS, ARDE means can causethat large features to be etched through earlier than small features, which may cause leakage of cooling helium fluid. Depletion of the fluorine content at the trench bottom is the root cause for ARDE.[97] The dominant process parameters are affecting RIE lag is thus SF6 flow rate and its dissociation.[66] The flux of radical species into the deep trench is key for etch kinetics, which is governed by Knudsen transport.[97] Depletion of the fluorine content at the trench bottom is the root cause for ARDE.[97] ARDE wasis also affected by pressure and temperature. It was reported that RIE lagARDE could also be improved by increasing pressure [98, 99] and decreasing temperature.[98] ARDE can cause large features to be etched through earlier than small features, which may cause etching on the layer beneath, or even leakage of cooling fluid for some applications. It should be noted that ARDE is not always undesirable:RIE lag is not generally preferred. However, some special applications intentionally make use ofr RIE lagARDE, such as the in deep silicon etches. F fabrication of slope electrodes is one example of this.[98100] Page 22 of 51 ARDE is a result of transport phenomena. The higher the aspect ratio, the more difficult it is to fortransfer reactants to reach the trench bottom and for transfer byproducts to escapeout of the trench. This mass transfer rate varies with etch progress, leading etch rate to decrease with etch progress. One strategy to overcome ARDE is to change the etch parameters as the etch progresses. Increasing the bombarding bias power gradually once the etch depth is deeper than a predetermined value was reported.[5459] Lower pressure tends to tighten the angular ion distribution, improvinge mass transfer to the bottom of the trench and consequently ARDE.[99101] Angular ion distribution may enhance the RIE lagI in high pressure plasma RIE tools the angular ion distribution is wider, thus ARDE is worsened.[100102] The mass transfer rate to the bottom of a deep trench bottom decreases significantly with the increasinges in aspect ratio. For a given set of process parametersAt a certain etch condition, the apparent etch rate will fall to zero at when aspect ratio increases to some maximum value of aspect ratio, there is no visible etch rate. This maximum achievable aspect ratio is known as the “critical aspect ratio.”[1021, 7875, 101103] Study shows thatB both model simulations and experimental results demonstrate that the critical aspect ratio dependsency on the relative flux of neutral species and ions at the trench opening and ionic mass transfer during the polymer etching step.[101103] The relationship between eEtch rate dependency onand aspect ratio is shown on Figure 6.[101103] Note that this model breaks down at very high aspect ratios. [103]ARDE, as an effect of mass transfer, is attributable to many parameters, mainly including topographical effects such as ion shadowing, charging, neutral shadowing, charging, and Knudsen transport of neutrals.[102104] When aspect ratio attains some value, apparent etch rate is a function of aspect ratio which follows the Knudsen transport model, such as the conductance model. This model has a deviation at the high aspect ratio regime.[101103] The etch rate depends on aspect ratio largely due to depletion of fluorine radicals and some re-deposition of passivation polymer. Both higher ion flux and ion energy are found to be critical to enabling the time-multiplexed etch process to attain a higher achievable aspect ratio.[1021] Efficient removal of the passivation layer at the trench bottom by adjusting the plasma chemistry also improves the achievable aspect ratio. [1021] <Figure 6 here>Page 23 of 51 Studies on ARDE at a variety of trench widths and lengths were conducted, reporteding that the etch rate was mainly determined by the trench width rather than by the length.[2641] This indicates that the etch rate is determined mainly by the shorter edge of the rectangular shape rather than by the area, although the length or area has some influences on the etch rate (, as shown in Figure 7).[2641] ARDE for different pattern shapes were also reported with similar results.[103105] <Figure 7 here>ARDE in a time-multiplexed silicon process was studied in detail by examining ARDE phenomena in three stages in of a process cycle: polymer deposition, polymer etch, and silicon etch.[104106, 105107] It was found that both deposition and silicon etch are aspect ratio dependent, with while both deposition and etch rates slow are reduced in smaller features. The polymer etch rate in the etch step is almost independent of feature dimensions. Based on these phenomena, a compensation method between deposition and etch was proposed by adjusting the relative times of deposition and etch steps at certain process conditions. Using this technique, a very small ARDE effect was obtained (2 to 3% across a width range of 2.5- to 100 m with 2 m/min etch rate).[104106] The Ccross- sectional SEM images of showinglow ARDE results are shown in Figure 8.<Figure 8 here>ARDE was also affected by pressure and temperature. It was reported that RIE lag could also be improved by increasing pressure [106, 107] and decreasing temperature.[106] Loading effects The lLoading effect is an etch rate variation phenomenon resulting from differences in pattern density, i.e. the area of exposed silicon.[102104] It occurs on both features of the same- size featuresand, but also on features with different dimensions. Reactant depletion is the root cause of the loading effect. When the the loading effect and ARDE occur together, investigation becomes difficult.Differences in etch rate between features over a small area on the wafer is referred to as mMicroloading. is a very common phenomenon in which etch behavior is affected by local loading. Owing to depletion of the reaction Page 24 of 51 radicals depletion, the etch rate decreases when the surrounding load increases. This introduces a critical distance beyond which etch rate is not significantly influenced by pattern density. It was reported that, under these experimental conditions, this critical distance was about 4.5 mm, and for an etch depth of 60 m, a 10% pattern density increase can cause a 1 m etch depth decrease in features within the critical distance at the experimental conditions.[7168] This is the main reason that little work has been done to understand pattern density dependencies for distances larger than 5 mm, known as “die-to-die” effects.[108] When bulk concentration is adequate, the loading at a specific location affects the consumption of reactants, causing etch rate changes. When pressure decreases, the consumption of reactants has less effect. It was reported that loading effects of silicon etch decrease at low pressure.[99101] Micrograss Micrograss is the term used for to describe the formation of micro-columns of silicon owing to the residual polymer left on the bottom surface after the etch process. ThereforeAn obvious, the first approach for remedying this might be to increase the bias power to remove the base polymer and then the grass, but. However, increasing bias power may have some side effects. Higher bias power may attack the passivation on the sidewalls, creating a bottling shape in the sidewall.[1114] By increasing the etch step length, micrograss can be controlled without creating sidewall profile issues.[1114] Other parameters that can be changed to reduce grass include temperature,[5459] ICP power, and pressure.[1114] When temperature is low (e.g. -10oC), the passivating layer deposition rate is high and its etch rate is low. These effects may cause micrograss, so higher temperature enhances the removal of micrograss.[5459] Micrograss is also influenced by feature size or aspect ratio because of the difference in passivating layer deposition. Compared with open areas, micrograss is less likely to occur in small features because of the difficulty of depositing the passivating layer. It was reported that at an 80 m etch depth, micrograss occurs on an open area, but not on the a 10m feature trench bottom of a 10μm wide features.[5459] Notching Originally notching was observed in etching silicon on insulator (SOI) for MEMS fabrication. In the TSV silicon etch application, an etch stop layer (commonly silicon dioxide and or aluminum) is used to prevent cooling helium leakage when the via is etched through.Page 25 of 51 Notching, also known as footing, is a common phenomenon in time-multiplexed etch processes, which produce a special lateral etch on the boundary between silicon and the underlying layer, as shown in Figure 9.[109] The reason is charge accumulation.[2641] It occurs only where silicon is underlain by a dielectric layer. Originally, notching was observed when etching silicon on insulator (SOI) structures for MEMS fabrication where the insulator layer is applied the back side of the wafer. In certain TSV applications, an etch stop layer (commonly silicon dioxide or aluminum) is used to prevent cooling helium leakage, which may introduce notching when wafer is etched through from the wafer susceptor that would occur if the via is etched completely through the wafer, leading to uncontrolled etch conditions.Notching becomes more severe when there is significant microloading, because the loading effect requires moderate overetch, where the etch continues for a certain time after the etch stop is exposed to allow complete clearing of the trench bottoms across the entire wafer. One technique to prevent notching is to increase the thickness of polymer during the period of overetch by increasing the length of the deposition step.[1114] Pressure is also an influential factor foralso affects notch formation. When pressure is increased, ion energy is reduced, resulting in a low sputtering rate of polymer, which reduces the notching.[14] <Figure 9 here>When pressure is increased, ion energy is reduced, resulting in a low sputtering rate of polymer, which reduces the notching.[11] Another method to control notching is to useapply intermittent, or pulsed bias low frequency (LF) pulse RF power to on the cathode.[110, 111] The process with LF pulse powerBias pulsing reduces the ionic charging at of the insulator beneath the silicon layer by allowing charge to dissipate during the “off” cycle, so that notching or footing on the bottom can be controlled.[110, 112, 113] When a conductive material such asor aluminum is used as an etch-stop layer, no notching occurs.[2641] Owing Because ofto ARDE, large features are etched through first. Overetch is necessary to etch all the features through. During overetch, plasma etches the exposed stop layer on etched-through features is etched. Because the stop layer is much thinner than the wafer, etch selectivity of silicon to the stop layer becomes very significant to Page 26 of 51 avoid etching -though of the stop layer. Therefore, it is required that the etch-stop layer underlying large features should not be penetrated before the etch depth in small features has reached the interface of the etch-stop layer.A two-step Other techniques to prevent notching include using two etch processes without bias pulsing has been reported requiring pulsed RF power on the cathode.[109] The first step etch uses thea time-multiplexed Bosch process to, etching as deep as possible without etching through. The second step completes the final small part of the trench using is a continuous etch using an etch gas (SF6) and a passivating gas (C4F8) together.[109] It should be noted that cCharge build-up during high aspect ratio etch is not always a problem. For example, i is a common phenomenon. In MEMS fabrication, notching has been used for in-situ releasing of a high aspect ratio beam.[114] 3. Steady-state etch processesReactive ion etch (RIE) In the early development of deep silicon etch, RIE was used in isolation, i.e. without any form or source plasma such as ICP. This produces an anisotropic etch, but the inherently low plasma density results in a low etch rate. was widely used because of its anisotropic properties. Given Because the plasma density dependsency on the bombardment strength in RIE reactors, producing a highly anisotropic etch conditions always produce requires strong bombardment, resulting in excessive PR erosion, forcing the use of either thick PR or low etch selectivity. Therefore, a hard mask (e.g. oxide mask) was generally used for deep silicon etch when RIE was used.[115] Passivating the trench sidewall is the most common strategy for high aspect ratio etch and it is a good strategy to passivate the sidewall by dissociating gas reactants in a plasma environment is a common strategy. In the early 1990s, it was reported that a mixture of SF6 and /C2ClF5 gas mixing was used for etch and passivation with to achieve aspect ratios of possibly up to 50 and silicon to PR selectivity (silicon to resist) of 28.[115, 116] Under the same etch conditions, more anisotropic trench profiles were obtained using a resist mask and thanisotropic trench profiles using an oxide mask.[115, 116] The possible reason was that more radicals containing carbon were generated during etching with photoresist than with an oxide mask, and which then reacted on the sidewalls to form polymeric films that impeded lateral etching.[115-117] Sidewall passivation using dissociation of reactants is more easily controlled than passivation by dissociation of resist because resist coverage and silicon coverage changes with the wafer patterns (loading) on wafers. For In the RIE mode, higher fractions of exposed silicon (high loading)coverage have lower selectivity.[116] After the SF6/O2 Page 27 of 51 sidewall passivation mechanism was known in 1980s, C2ClF5/SF6 mixing for sidewall passivation was reported, resulting in anisotropic etch without undercut. However, the selectivity for this RIE etch was low, and thick resist had to be used.[116] It was reported that adding oxygen or hydrogen resulted in higher trench surface roughness. Conversely could be worse when oxygen was added to SF6 gas or the hydrogen content was increased in SF6 in the RIE condition, but the surface could become smooth with decreased power and or increased pressure would produce smoother surfaces.[118] Cryogenic Etching at cryogenic condition The cIn 1988, the cCryogenic process attempts to was proposed, which, at that time, separately controlled the etch reactions on trench bottom and sidewall surfaces separately with and achieve high silicon etch rate and a high silicon-to-resist selectivity by lowering the sample electrode (cathode, and hence the wafer,) temperature. [2913] Before the invention of the cryogenic process, the fine-etched profiles of silicon were obtained with low selectivity and low etch rate. To etch silicon with an acceptable profile,, although thick resist mask had to be used in 1980s, limiting the application of the deep silicon etchwas used. The main etch propertiescharacteristics of the cryogenic processes are shown in Figure 10.[2913] A high aspect ratio silicon trench created using a cryogenic etch process is shown in Figure 11.[119] <Figure 10 here>Figure 10 indicates clearly that the silicon etch rate increases and photoresist etch rate decreases when temperature is reduced, especially below -100oC. Good anisotropy without silicon undercut was achieved when temperature dropped below -100oC. Therefore, cathode temperatures below -100oC became the main process window parameternorm for cryogenic etch and this figure condition became the starting pointserved as a good guideline for further process optimization.<Figure 11 here>Page 28 of 51 However, low temperature alone cannot guaranty anisotropy. Even at temperatures below -120oC, isotropic etch was obtained.[120] After the addition of oxygen, anisotropic etch was generally obtained. Sidewall passivation plays an important role in reducing the lateral etch. It was reported that ion bombardment might dominate the cryogenic etch process in most cases, rather becausethan surface chemical reaction rates are greatly reduced by the low temperature.[121] The cryogenic process is an important method for high aspect ratio silicon etch. It uses SF6 and O2 gases to passivate and etch simultaneously. The passivation film consists of SiOxFy. Compared with Teflon-type polymer passivation found in the time-multiplexed process, SiOxFy passivation film is more difficult to etch, requiring high bombardment energy to ensure clear the polymer from the trench base ( bottom) surface and allow vertical silicon etch without visible lateral etch. The Although higher bombardment energy may generally increases the resist etch rate, the low temperature found . However, in the cryogenic process ensures that, a low resist etch rate is observed at low temperatureachieved (i.e., below -100oC). An important advantage of cryogenic processing is its low sidewall surface roughness.The cryogenic process has a high etch rate when feature sizes areis larger than 1 m.[7088] When SiO2 is used as a hard mask, a selectivity of 750 can be achieved.[7088] Temperature and oxygen flow rate are the the two key parameters responsible for the profile. A decrease in oxygen flow will reduce the passivation, enhancing isotropic etch. Conversely, too high an oxygen flow rate may cause a “pinch-off” of the trench, where at some particular depth, formation of oxide at sides of the trench bottom causes an abrupt narrowing of the trench. Reducing the tTemperature reduction tends to produce more passivation and improve profile verticality.[7088] Increasing the bBias power or reducing the pressure influence is clearboth make the sidewall profile : the higher the bias power, the more vertical the sidewall profile. Pressure changes function similarly, with lower pressure resulting in greater verticality.When photoresist is used as a soft mask, selectivity is a challenge for cryogenic processing. SomeA modified resist modified by gallium ion implantation and then was proposed to increase the selectivity. Gallium-ion- implanted resist is oxidized to form a gallium oxide was developed, which improveds the etch selectivity significantly. GOther alternative cryogenic processes uses gallium-ion-implanted silicon has also been used as an etch mask, which can to etch the silicon substrate.[52] This process can produce high aspect ratio features as small as 40 nm. .[5215] An example recipe for the cryogenic process is: 60sccm SF6 flow rate of 60 sccm, 13sccm O2 Page 29 of 51 flow rate of 13 sccm, 600W ICP power of 600 W, 5W RIE power of 5 W, 10mTorr pressure of 10 mTorr, and temperature of -115 oC, withresulting in an etch rate of 2.85 m/min.[122]Cryogenic processing uses a hardware configuration similar to that of the time-multiplexed etch process except that helium or liquid nitrogen is used for cooling the back side of the chuck to keepto cool the wafer temperature below -100oC. The etch chamber usually consists of ICP coils for plasma generation and a cathode for bombardment control. When photoresist is used as a soft mask, selectivity is a challenge for cryogenic processing. Some modified resist was proposed to increase the selectivity. Gallium-ion-implanted resist is oxidized to form a gallium oxide, which improves the etch selectivity significantly. Other alternative cryogenic processes uses gallium-ion-implanted silicon as an etch mask to etch the silicon substrate.[52] This process can produce high aspect ratio features as small as 40 nm. It was reported that dDeep silicon trenches were was also etched at under cryogenic conditions using an electron cyclotron resonance (ECR) plasma process in an SF6 and Ooxygen2 gas environment.[122123] The etch rate decreased significantly with an increase in oxygen flow rate, and the fluorine/oxygen ratio played ans important role in varying the etch profile from a positive to a negative slope.Besides ICP and electron cyclotron resonance (ECR) plasma, dDeep silicon trench was also etched byA a helicon plasma reactor using helium and liquid nitrogen for cooling has also been used.[123124] For a 2 m wide, 50 m deep trench, a 5 m/min etch rate was obtained. The wafer surface temperature strongly affected the profile with low temperature having better anisotropy. HoweverNote that, there was still a temperature difference of 10oC between the chuck and the wafer is common, , even though helium and liquid nitrogen cooling was used.[123124] Cryogenic etch is not widely used today because of the practical difficulty of maintaining the very low wafer temperature. The reactor hardware is complex, and the time taken to cool the wafer down from ambient Low pressure also gave better control of anisotropy.An example recipe for the cryogenic process is: SF6 flow rate of 60 sccm, O2 flow rate of 13 sccm, ICP power of 600 W, RIE power of 5 W, pressure of 10 mTorr, and temperature of -115oC, with etch rate of 2.85 m/min.[124] temperature for processing, and back to ambient after processing results in a very slow process with low manufacturability.Page 30 of 51 Near-Room Temperature High Density Plasma Etch Simultaneous etch with passivation A simultaneous etch and passivation process at ambient temperature using RIE was pursued with very limited In an effort to overcome the shortcomings of the RIEI-only and cryogenic approaches, reactors using two plasma sources, e.g. ICP and RIE, were explored at room or near-room temperatures.success. The use of chlorine instead of fluorine as the etch gas was also explored, because the lower reactivity of Clchlorine results in less sidewall erosion.In the 1990s, ECR high density plasma using 2.45 GHz microwave power found application in near-room temperature high density plasma (HDP)high aspect ratio silicon etch.[99101, 125, 126] This process usede high density plasma dissociated chlorine gas to form radicals and a 13.56 MHz bias electrode to controlled bombardment strength. However, the lower reactivity of cClhlorine results in lower etch rate, even with strong The relatively low etch rates process using chlorine gas, andalthough the etch rate dependsence on bombardment. So although the etch profile was good, the low etch rate strength, made the deep silicon etch feasible for practical use, but the etch rate was stillseems too slow (i.e., 0.31 µm/min or less) made this process unsuitable for volume manufacturing. In 1998,Cl2 was used in an RIE-ICP etch tool for micromachining a silicon field emitter and high aspect ratio resonators with controlled profiles and high aspect ratios. In this application, the low etch rate problem wasmight not be a problem acceptable.[127] SinceInIn 20020,, a steady-state etch process was reported that used HBr and O2 for passivation and SF6 for etch.[6982, 128] HBr alone and SF6/HBr/O2 together were examined using an ICP-RIE configuration, HBr only the former etch gas having a lower etch rate. The process window conditions using SF6/HBr/O2 waswere: pressure of 10- to 30 mTorr, 600-1000W source ICP power of 600 to 1000 watts, 15-44W bias RIE power of 15 to 55 watts, (SF6+O2)/HBr ratio of 1 to 3, and total flow of 170 sccm. This process showed a high etch rate (>3 m/min) and good trench depth uniformity (non-uniformity < 1%). Trenches from he 10.6 to- 10 m wide, 7 m deep trench etched by this process is shown in are Figure 12.[69129] The trench profile is very <Figure 12 here>Pressure is a sensitive parameterto pressure, with a for trench profile control and higher pressure givinges a more tapered sidewall profile. The primary reason for this trend is that higher pressure increases sidewall polymer Page 31 of 51 deposition. However, hHigher pressure may increase trench depth non-uniformity by worsening plasma non- uniformity at higher pressures condition.SF6/O2 ratio is a sensitive parameter for etch rate and trench profile. High SF6/O2 ratio tends to haveresult in high etch rate and vertical profile, mainly because the high ratio relatively increases etchant species (fluorine) and reduces passivantpassivating species (oxygen). However, if the ratio is too high ratio value will enhance silicon lateral etchattack (isotropic etching) will occur and reduce the selectivity will decrease. TooH high bias power also reduces the selectivity.It was found that a very high source power can stop the etch process stops completely.[82] The mechanism may be that high power increases a fast silicon surface oxidation comparedat the expense with silicon-fluorine reactions etch by fluorine chemicals. This effect can be mitigated by increasing the fluorine content (raising the SF6/O2 ratio), increasing the ion energy (biasRIE power), or both.A high aspect ratio result using this method The best result obtained to date using simultaneous etch with passivation is aTill now, trench with about 90:1 aspect ratio and 90 nm CD ( was obtained by using simultaneous etch with passivation, as shown in Figure 13).[130] Besides this configuration,A process AnotherICP-MERIE configuration study using the same etchants but different etcher configurations (ICP and MERIE) was reported for MEMS applications. In this case, however, a magnetically-enhanced RIE bias power system was used in combination with an ICP source.[114] <Figure 123 here>Yet another simultaneous etch and passivation process used the same gases with as thea time-multiplexed etch process, SF6 and C4F8. [109, 129] When etch gas and passivating gas are introduced into the plasma chamber together, the etch and passivation occur simultaneously. This makes it possible to find a process window conditions in which an anisotropic profile can be obtained, as shown in Figure 14. Variety of HoweverT, he desired pFigure 1 shows profiles were obtainedcan be chosen changes by varying the ratio with the addition of passivating gas (C4F8) to etch gas (SF6) for silicon etch in an ICP-RIE plasma, as shown in Figure 15 for an ICP-RIE reactor.[109] <Figure 153 here>Page 32 of 51 Figure 15 shows that Tthe profile changes with the ratio of C4F8 to SF6, from isotropic etch profile at 0% C4F8 (Ffigure 15a) to anisotropic vertical profile at 75% C4F8 (Ffigure 15f). The disadvantage of this process is the a low etch rate (about 1.6 m/min.[109] With the improvement of the etch reactor and the process to increase etch rate, this steady-state etch may have a promising future in MEMS and TSV applications where moderate sidewall slope makes bulk metal fill easy. The etch profile with some slope may be more suitable to some applications that need filling of the holes.In 2004, SF6 and oxygen O2 gas was were used for steady-state high aspect ratio silicon etchHAR silicon etch, with achieving a vertical profile, 20:1 aspect ratio of 20, and 1.3µm/min etch rate of 1.3 µm/min on for 0.35 µm holes. It was found that the etch rate was determined by the fluorine-to-ion ratio and influenced by pressure, with a maximum etch rate occurring at 25mTorr.[128131] At high pressure, the fluorine-to-ion ratio is high, so the etch rate is ion-limited, and at low pressure, the fluorine-to-ion ratio is low, so the etch rate is neutral-limited. The synergy results in a maximum etch rate at pressure of 25 mTorr at the experimental conditions.[128] Profile is mainly determined by the fluorine-to-oxygen ratio. A high fluorine-to-oxygen ratio tends to produce isotropic etch and vice versa. Recently, simultaneous etch with passivation has obtainedmade significant progress in terms of etch quality and etch rate. With more strict requirement on the TSV sidewall roughness specifications are becoming more stringent, so more attention is being paid onto this technology, making it a strong competing alternative method to currently popular time-multiplexed process. 4. Etch method and equipment Reactor designs differ mainly in Etch technology is dependent on the plasma generation method. PlasmaCommon methods are is mainly generated by ECR, ICP, helicon wave, helical resonator, microwave surface wave, and capacitively coupling, most of which. Till now, most of these plasma generation methods have have been examined for high aspect ratioHAR silicon etch. Plasma etch for high aspect ratio silicon trench has major advantages over wet etch, hence dry etch for high aspect ratio silicon trench is currently the predominant method. Very earlyThe first reactorsoriginal plasma etch used two parallel plates. The , one of which (usually the lower one usually) held the etch samplewafer. The 13.56 MHz RF power, chosen because of its wide availability, was capacitively coupled to either the upper or lower electrode. The former configuration is commonly called plasma Page 33 of 51 etch mode (PE) mode and the latter one reactive ion etch mode (RIE) mode. The main difference between these two modes is the bombardment strength, with RIE having . In PE mode, sample stronger bombardment is not as strong as in RIE mode, which results inand hence lower selectivity for RIE mode. The rise in temperature owing to the relatively strong bombardment in RIE mode further reduces RIE mode selectivity even more. By Uusing a parallel capacitively coupled plasma (CCP) in with SF6/CHF3/O2 gases, an etch rate of 2.5- to 2.8 m/min was reported, but the anisotropy was only 0.5 (see Ffigure 10), insufficient for most MEMS and TSV applications.[129132] It was reported that a magnetron reactive ion etch (MRIE) tool with a rotary cathode (manufactured in-house) was used for deep silicon etch, achieveingd a submicron high aspect ratio pattern but at a low 0.3μm/min etch rate.[130133] However, the etch rate of 0.3 µm/min seems too low. In another study, the an RIEI reactor, with a magnetic field and a narrow gap between the electrodes in the RIE reactor was used to increase plasma density, achieved for an etch rate of 1.6 µm/min.[131134] In another experiment, tTo achieve a high etch rate, ferro-magnetic materials were inserted inside the pedestal of an RIE reactor, producing a 10 µm deep trench of for a sub-micron capacitor at an etch rate of 6 µm/min in 1992.[1548] To increaseFor a high etch rate, more etch radicals must be produced by dissociation in the plasma. This dissociation depends on plasma density. The phenomenon was understood in the 1980s and since then strategies for improving high aspect ratio silicon etchHAR silicon etch have been to decouple the bombardment energy and plasma density with a variety of chemicals to improve the anisotropy for high aspect ratio. Another approach is to lower temperature to increase selectivity and anisotropy by sidewall passivation at a steady-state condition. The etch rate challenge for deep silicon etch prompted use of high density plasma in the etcher. Combined with RIE, several high density plasma generation methods were investigated, including ICP, magnetron ion etch (MIE), MRIE, [130133] microwave ECR,[99101, 125] as well as magnetic neutral loop discharge (NDL).[132135] Etch tool The reactor configuration is related driven by the evolutions of theto etch process evolution., and corresponds to the etch process and chemistry. A dc DC plasma discharge confined by multi-polar magnetic surface layer was reported in 1985 using SF6 and O2.[133136] Later Iin 1992, a comparison of deep trench silicon etching using MIE and RIE in SF6/O2 plasma was reported.[134137] It The study showedshows that RIE produces a smoother trench surface while the MIE shows better sidewall angle performance in sidewall angle and etch rate at the experimental conditions.[134137] Page 34 of 51 Before cryogenic processing was proposed in 1988, processes developed using microwave plasma, electron cyclotron resonance (ECR) plasma, and magnetron-type RIE had were force to make compromised to trade off between anisotropy, and selectivity, and sometimes between selectivity and the etch rate.[2913] Both RIE and ECR can achieve anisotropic profiles, but the etch rate is usually low when aspect ratio increases. By using cryogenic processing, and SF6/O2 etchants and SiO2 hard mask in a helicon reactor, an aspect ratio of 20 to 50:1 and with an etch rate of 5 m/min were was reported in 1999.[119] The helicon plasma source was proposed in 1982 and was widely studied.[119, 135138] Its main advantages are high plasma density, independent control of plasma density and ion energy, and low-pressure operation. In the mid-1980s, a multi-polar helicon plasma source discharge was used for anisotropic silicon etching in a SF6 and oxygen system.[133136, 136139] In all cryogenic process configurations, the cryogenic chuck using liquid nitrogen and helium has to be used for cathode temperature adjustment from 20oC down to -150oC.Since the mid-1990s, the ICP-RIE configuration has come to dominate high aspect ratio silicon etchHAR silicon etch (Ffigure 16). The main advantages of this configuration is areits simplicity, low cost, and good process stability allowing straightforward process optimizationeasy control. Currently, etch tools with this configuration are the main work horses for high aspect ratio silicon etch. A typical ICP-RIE etcher configuration is shown in Figure 16.<Figure 16 here>There is no systematic comparison among different etch tool configurations, but there was it wasa reported that states that MRIE etch rates of silicon substrate were insensitive to the loadingopen ratio in the range of from 10 to 50%, in contrast to ICP etching at their experimental conditions.[114] However, the etch rate of this MRIE configuration was rather low. Although many characteristicsProcess can be improved by optimization, but some tool design issues, such as tilting trench, have can only beis mainly solved by modifying the reactor hardwareto be solved by tool manufacturers. Page 35 of 51 5. Theoretical analysisThermodynamics The first and most important use of thermodynamics is to determine the overall reaction products and spontaneity at theunder predetermined conditions, more specifically, the undercondition of constant pressure and temperature. Gibbs energy change analysis is the a well known method. For high aspect ratioHAR silicon etch, theoretical analysis is focused on etch and passivation.High aspect ratioHAR silicon etch generally uses fluorine-containing chemicals (e.g., such as SF6, ) for etch owing to good byproduct volatility, and C4F8 for sidewall passivation. Cl2 chemistry for silicon etch exhibits a slow etch rate, [4434, 137140] and low selectivity to SiO2 hard masks and lower byproduct volatilitying.[138141] Br- containing gases also have also been used, silicon etch capability, but byproduct volatility and etch rate are is even worse than for chlorine-containing gases. Also, the etch rate is too low compared with fluorine-containing chemicals.[139142] Mixturesing of CIF3 and SF6 were also studied in the early 1990s, but detailed follow-up data are lacking.[140143] Besides SF6 gas, NF3 and SiF4 were studied and proved to have a high etch rate, but HCl, HBr, and SiCl4 result demonstrated betterin more anisotropy with at the expense of a relatively low etch rates.[141144] Oxygen is helpful in building the passivation layer on the sidewall, but too high an oxygen flow rate will produce very thick passivation on the trench bottom which is difficult to etch, resulting in a low, or even zero, etch rateits thickness needs to be well controlled. For steady-state ICP-RIE deep silicon etch, SF6/HBr/O2, XeF2 and BrF3 were investigated.[6982, 142145, 143146]However, t To date, there is no systematic comparison among between these fluorine-containing gases, and SF6 is the most popular gas for high aspect ratioHAR silicon etch. A computer program model using the Gibbs energy minimization (GEM) method to determine the reaction products and spontaneity was reported.[144147] By using GEM, overall silicon etch reactions were obtained for different reactants. When silicon is etched by SF6 gas at 20 mTorr pressure, we have the following overall spontaneous etch equations: o Si  2SF6(g )  SiF4( g)  2SF4(g) T  100 CPage 36 of 51 o 2Si  2SF6(g)  2SiF4(g)  S2F2(g) T  30 CThe equations shows that all byproducts are volatile and silicon-containing product iss are SiF4 gas, but the o sulfur-containing products depend on temperature. When temperature is above 100 C, the equilibrium product is SF4 o o o gas, but when it is less than -30 C, the product is S2F2 gas. From In the temperature range of -30 C to 100 C, both products can exist. When NF3 gas is used for silicon etch at constant pressure and temperature conditions, the overall spontaneous etch reaction is:3Si  4NF3(g)  3SiF4( g)  2N2(g )It is generally believed that atomic fluorine is the reactionve radical, but at room temperature both SF6 and NF3 are thermodynamically stable gases. The plasma environment is may be responsible for dissociating the reactants to form reactive radical, i.e. the atomic fluorine.Several chemicals function as passivating agents among which. octofluorocyclobutane (C4F8) is a very common one. During sidewall passivation, octofluorocyclobutane (c-C4F8), a cyclic fluorocarbon, breaks down in the plasma to produce CF2 and longer chain radicals in the high density plasma.[1114] These radicals are believed to be responsible for polymerization on sidewall and base surfaces.C4F8 (octafluorocyclobutane) is a perfluoro carbon (PFC), which is not an environmentally friendly gas. Therefore, use of environmentally benign gases, such as unsaturated fluorocarbons (UFC), was reported.[7673] Deep silicon etching using SF6/C4F8 and SF6/C4F6 was were compared, showing different performance.[1114, 8279] C4F6 gas can produce thicker, more strongly bonded fluorocarbon films than C4F8 because more CF2 radicals and lower F/C ratio fluorocarbon films were generated in the C4F6 plasma, according to OES and XPS measurements.[7673] However, it is difficult to obtain the overall passivation reaction owing to the lack of thermodynamic data on organic compounds.The spontaneity of the polymerization depends on the overall Gibbs energy change in the process, resulting from volume and surface Gibbs energy changes and surface Gibbs energy change, the former being negative and the latter positive. [145148] Page 37 of 51 The oOriginal condensed polymer particles (seeds) should must be larger than a certain size before enough to ensure the spontaneous reactions will occurity. However, pPolymer is difficult to form in gas phase, because of the surface Gibbs energy. ConverselyI, itt is much easier to form polymer starting aton a surface, such as a feature sidewall or trench bottom, because of the to lower reduce the surface energy. Thermodynamic parameters are keys to the spontaneity of polymerization. The most important is temperature, with low temperatures the most favorable. Thermodynamic etch reaction products are also helpful for determining kinetic mechanisms and rate equations formulae express. Unfortunately, there is insufficienta lack of data forto determine proving the byproduct compositions for etch and passivation reactions.Kinetics and simulations Plasma etch kinetics is focused on etch rate and mechanism. Consequently, understanding and measuring radicals of elementary reactions radicals in a plasma environment become critical. Experimentally, it is very challenging to measure densities of ions and reactive radicals densities. Generally, ion density is measured using a Langmuir probe and densities of free radicals are estimated using an optical emission spectrum. In a time- multiplexed etch process with passivation, the polymerization characterization is also important to the overall process. It was reported that the polymer layer deposition and sputtering were also monitored with in situ ellipsometry.[1021] The reaction mechanism in a time-multiplexed etch process was studied and the following dissociation reaction proposed:[91]    SF6  e  SF5  F  2e + where atomic fluorine and heavy particle SF5 are the dissociation products in the plasma environment. The silicon etch reaction is:[91] Si(s)  4F(g )  SiF4(g)The passivation is caused first by the dissociation of C4F8:[91] Page 38 of 51   C4F8  e  C3F6  CF2  eThen CF2 is adsorbed on a solid surface to form a Teflon-like polymer on the solid surfaces:[91] nCF2  (CF2 )nIt should be noted that aAlthough the etch mechanism was proposed in above equations is plausible, there is no direct proveproof for this assumption.In high aspect ratio silicon etch, the most important control variables are ion-to-radical ratio and bombardment strength. The kinetics of etch reaction and polymerization are helpful in improving the etch process and increasing the overall etch rate. Because polymerization contributes negligibly to the overall etch rate, it is preferred to have a fast polymer deposition and long etch time to obtain a high etch rate.Polymerization consists of two steps: a. First is the gaseous reaction in the plasma environment to form the gaseous monomers for the polymer and second the polymerization itself, also called theis the monomer entering condensation phase, similar to crystallization processes of the nucleation and growth process. When plasma density and chemical flow rate are sufficiently high enough, mass transfer may be the rate control step may be the second step. Kinetically, lower temperatures result in more seeds to grow polymer. The overall polymerization rate depends on the seed creation rate of seeds and the seed growth rate from a single seed. When the seed creation rate rather than growth rate is a control step, the overall polymerization rate will increase with the decrease in temperature (, as shown in Figure 147).[5459] When the polymer deposition rate is too high, micrograss results (Ffigure 17a). Conversely, too little polymerization results in undercutting from isotropic etch (Ffigure 17c).<Figure 147 here>High aspect ratio siliconE etch rate is determined by radical formation in plasma, mass transfer from bulk plasma to trench surface, and activation on the reaction surface. The mass transfer in deep trench is believed to be Page 39 of 51 the rate-control step, usually described by the conductance model.[3116, 103105] Average etch rate inover one etch /passivation cycle in the time-multiplexed process, by definition, can be expressed as: [106]   r  r  r 1 d 1 d  A e   r    p  where re is silicon etch rate at the trench bottom; d and  are passivation and overall time durations in one cycle; rd and rp are polymer deposition rates during the in passivation step and polymer etch rate induring the etch step, respectively. ObviouslyClearly, the etch rate, rA is a function of aspect ratio because all re, rd, and rp are all determined by aspect ratio.Assuming that the With the assumption of etch rate is proportional to the flux of reactant flux, followingthe etch rate equation induring silicon etch step can be expressed as:[19] K  re  reo    K  S  KS  where reo is silicon etch rate at zero aspect ratio; K is transmission probability, i.e. the probability that a randomly directed moleculeparticle incident on one end of a tube will exit the other end; and S is the reaction probability. K is a function of aspect ratio. TComparison between the model and experimental results are in on silicon etch is shown in Figure 158, indicating good agreement (Ffigure 18).[103105] For rate equation on the time multiplexed process, the polymer deposition and etch rates are also dependent on aspect ratio, but there areis no satisfactory equation no satisfied solution for them so far.<Figure 158 here>Mass transfer to the trench bottom is a function of aspect ratio. It was reported that the fluorine-containing ion current decreases with an increase in aspect ratio.[146149] This relationship of between ion current versus aspect ratio follows the agrees withsame trend as etch rate versus aspect ratio, which suggestsbut it ishas not been proved Page 40 of 51 yet that fluorine-containing ion current plays an important role in high aspect ratiodetermining the silicon etch rate. + + + + When C4F8 was used for high aspect ratio silicon etch, the ion energy distribution (IED) of CF , CF2 , CF3 , and CF4 was experimentally measured.[146] Three components determine the cChemical reaction rates in plasma environments: consist of three contributions, i.e., physical sputtering rate, chemical reactions rate, and ion-assisted reaction rate. To maintain high selectivity of etched material to photoresist, bias power and physical sputtering rate should be kept very lowminimized. Therefore, anisotropic etch is mainly determined by the etch rate balance between chemical reaction and ion assisted etch rates at the trench bottom and sidewall.Chemical etch reaction at the sidewall is strongly dependent on the temperature, according to kinetic theory. Because average ion incidence angle to the bottom surface deviates only a few degree from normal, ion assisted etch on the sidewall is relatively small compared with bottom etch. Hence sidewall etch rate is mainly determined by chemical etch rate and decreases with temperature. However, the bottom etch rate behaves differently. Owing to the almost vertical bombardment, ion assisted etch rate at the trench bottom plays a much more important role than on the sidewall, especially when temperature decreases. This mechanism indicates that a decrease in temperature causes a significant reduction in sidewall etch rate reduction on the sidewall, but not on the trench bottom. However, only reducing temperature cannot guaranty the HAR silicon quality. Partial oxidation of trench sidewall by producing SiOxFy passivation layer enhances the sidewall etch control.[14] This explains why cryogenic etch processing can improve feature anisotropy with at high aspect ratios. Etch kinetics at ambient temperature or near room temperature become more and more important owing to the fact that this HAR etch method has advantages such as smooth sidewall angle, high aspect ratio, high selectivity, and easy operation for production. Current etchant is generally SF6/O2/SiF4. Because of the relatively high oxidation rate of silicon at room or near room temperature compared with cryogenic process, strong bombardment is required to obtain a moderate etch rate at trench bottom, which may cause a high photoresist erosion rate. At well controlled etch conditions, a modified layer on top of photoresist can be formed, which reduce the photoresist erosion rate, resulting in an acceptable etch selectivity. 6. Conclusions High aspect ratio or deep silicon etch has been employed in many applications since the very early days of silicon etch in the 1970s. Currently, deep silicon etch is used mainly for MEMS and TSV applications. It is Page 41 of 51 predicted that TSV etch will become a very critical process for 3-D IC stacking technology. Other applications include deep silicon etch for memory chipDRAM capacitors. Before 1990, anisotropic Anisotropic silicon etch had limited applications and the high aspect ratio etch process was in the research and development stage before 1990. Three inventions played important roles in deep silicon etch. One wasT the high density plasma environment realized by introducing the ICP-RIE configuration, which. This kind of etcher design enabled decoupling independent control of plasma density and bombardment strength controls. Second Cis the invention of cryogenic processing, which made deep silicon etch practical as an industrial practice. Even though the achieving a waferlow temperature below -100oC is costly and makes process control complicated and costs high, this process has some special etch properties, such as steady-state process control and smooth sidewalls, i.e., low trench sidewall surface roughness which are. This property is essential for some applications. Lastly, The third and also very important invention is thethe time-multiplexed process, i.e., the Bosch process, which repeats pairs of passivation-etch steps to obtain high aspect ratios and straight sidewall profiles. An Iimportant advantages areis its high etch rate and selectivity, although it the time-multiplexed process suffers the intrinsic disadvantage of scalloped sidewalls and high sidewall surface roughness. Since its introduction, many process modifications have been proposed to overcome this drawback. Besides above three inventions, gradual progress on single step etch at room or near room temperature using SF6/O2 as well as other gases proves today that this approach has many special advantages (e.g. smooth trench sidewall, high etch rate and selectivity). The performance makes this method have good application potentials. MMany challenges remain although much progress has been made in deep silicon etch over the last twenty years, but challenges remain. In TSV etch, fFurther increases in etch rate are always needed for large volume production, especially for TSV etch. Other challenges include controlling sidewall roughness control, tilt control, sidewall angle, microloading, notching, micrograss, and ARDE. In the future, much more fundamental work will be necessary to s are needed for meet theing increasing demands on high aspect ratioHAR etch. Mechanisms onThe etch and passivation mechanisms are not well understood well now and practical rate equations for practical uses need to be established. Progresses in these areas will allow higher throughput processing and lower costs, critical benefits in the have critical influences to semiconductor industry in terms of throughput and costs.Page 42 of 51 Acknowledgement The authors would like to thank Richard Lewington of Applied Materials for his editorial contributions to this paper.References 1 K.E. Bean, “Anisotropic etching of silicon,” IEEE Transactions on Electron Devices, ED-25, 1185-1193 (1978). 23 X. Li, T. Abe, Y. Liu, and M. Esashi, “Fabrication of high-density electrical feed-through by deep-reactive-ion etching of Pyrex glass,” J. Microelectromechanical Systems, 11, 625-630 (2002). 243 B. Tan, “Deep micro hole drilling in a silicon substrate using multi-bursts of nanosecond UV laser pulses,” J. Micromech. Microeng., 16, 109-112 (2006). 254 S.J. Kwon, Y.M. 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Appl. Phys., 39, 1367-1370 (2000).Page 49 of 51 Captions of figuresFigure 1. Schematic of Bosch method. (a) sidewall passivation using C4F8, (b)silicon isotropic etching using SF6 gas,(c) SEM image of deep trenches, (d) magnified SEM image of the sidewall with nanoscallopsFigure 2. Etch rate as a function of the C4F8 flow for several passivation pulse times at a given etching pulse (a) at the encircled points the profile is anisotropic and the etch rate goes down. These points have been drawn in a C4F8 flow vs. inverse passivation pulse time plot (b). It gives a linear relation dividing regimes of isotropic etching and polymer deposition. At the boundary of these regimes, etching is anisotropic.Figure 3. Optical emission spectroscopy results during C4F8 polymerization, (a) low pressure and high power plasma, (b) high pressure and low power plasma. Figure 4. Polymer deposition rate comparison in C4F8 and C4F6 plasma at the same condition.Figure 5. Arrays of vertical silicon (100) nanopillars. (a) Silicon nanopillars as narrow as 40 nm diameter and 1.5 um tall with vertical sidewalls arrayed on an ordered 235 nm pitch grid. (b) Higher magnification view showing sidewall roughness less than 10 nm peak-to-peak. (c) Wide field view showing a large area array with long range order.Figure 6. Conceptual depiction of (a) the evolution of the depth of silicon trench as a function of time, and (b) apparent etch rate versus aspect ratio.Figure 6. Conceptual depiction of (a) the evolution of the depth of silicon trench as a function of time, and (b) apparent etch rate versus aspect ratio.Figure 7. Etch Trench depthrates versus trench width and lengthFigure 8. The effect of RIE lagsARDE at under different process conditions with on features with widths range from2.5- to 10 m, (a) normal ARDE lag (~10%), (b) optimized ARDE lag (<2%), and (c) inverse ARDE lag (-5%).Figure 9. Notching observed at the interface between the silicon and the SiO2 layer.Figure 10. Etch properties at cryogenic processesFigure 11. Cross sectional SEM image of silicon etch by using helicon reactor with cryogenic process (1999)Figure 12. High aspect ratio trench of 1 m wide and 7m using one step silicon etching sampled at wafer center (left) and edge (right) Page 50 of 51 Figure 13. High aspect ratio trench etched by a single step etch process at near room temperatureFigure 14. A MEMS part with a vertical profile etched by a single step etch process at near room temperatureFigure 15. Profile changes with C4F8 contents balanced with SF6 in a steady state silicon etching, (a) 0% C4F8, (b) 10% C4F8, (c) 20% C4F8, (d) 30% C4F8, (e) and (f) 75% C4F8.Figure 164. Diagram of a typical ICP-RIE reactorFigure 17. Polymer deposition rate versus temperatureFigure 185. Comparison between model-calculating and experimental results.Page 51 of 51

High Aspect Ratio Silicon Etch - a Review

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