VxWorks Architecture Supplement VxWorks® ARCHITECTURE SUPPLEMENT 6.2 Copyright © 2005 Wind River Systems, Inc. All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means without the prior written permission of Wind River Systems, Inc. Wind River, the Wind River logo, Tornado, and VxWorks are registered trademarks of Wind River Systems, Inc. Any third-party trademarks referenced are the property of their respective owners. For further information regarding Wind River trademarks, please see: http://www.windriver.com/company/terms/trademark.html This product may include software licensed to Wind River by third parties. Relevant notices (if any) are provided in your product installation at the following location: installDir/product_name/3rd_party_licensor_notice.pdf. Wind River may refer to third-party documentation by listing publications or providing links to third-party Web sites for informational purposes. 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Corporate Headquarters Wind River Systems, Inc. 500 Wind River Way Alameda, CA 94501-1153 U.S.A. toll free (U.S.): (800) 545-WIND telephone: (510) 748-4100 facsimile: (510) 749-2010 For additional contact information, please visit the Wind River URL: http://www.windriver.com For information on how to contact Customer Support, please visit the following URL: http://www.windriver.com/support VxWorks Architecture Supplement, 6.2 11 Oct 05 Part #: DOC-15660-ND-00 Contents 1 Introduction .......................................................................................... 1 1.1 About This Document ........................................................................................... 1 1.2 Supported Architectures ....................................................................................... 2 2 ARM ....................................................................................................... 3 2.1 Introduction ............................................................................................................. 3 2.2 Supported Processors ............................................................................................ 4 2.3 Interface Variations ................................................................................................ 4 2.3.1 Restrictions on cret( ) and tt( ) ............................................................... 4 2.3.2 cacheLib ..................................................................................................... 5 2.3.3 dbgLib ........................................................................................................ 5 2.3.4 dbgArchLib ............................................................................................... 6 2.3.5 intALib ....................................................................................................... 6 2.3.6 intArchLib ................................................................................................. 6 2.3.7 vmLib ......................................................................................................... 7 2.3.8 vxALib ....................................................................................................... 8 2.3.9 vxLib ........................................................................................................... 8 iii VxWorks Architecture Supplement, 6.2 2.4 Architecture Considerations ................................................................................. 8 2.4.1 Processor Mode ........................................................................................ 9 2.4.2 Byte Order ................................................................................................. 9 2.4.3 ARM and Thumb State ............................................................................ 9 2.4.4 Unaligned Accesses .................................................................................. 9 2.4.5 Interrupts and Exceptions ....................................................................... 10 Interrupt Stacks ......................................................................................... 10 Fast Interrupt (FIQ) ................................................................................. 11 2.4.6 Divide-by-Zero Handling ....................................................................... 11 2.4.7 Floating-Point Support ............................................................................ 11 2.4.8 Caches ........................................................................................................ 12 2.4.9 Memory Management Unit (MMU) ...................................................... 13 Cache and Memory Management Interaction ..................................... 14 BSP Considerations for Cache and MMU ............................................. 15 2.4.10 Memory Layout ........................................................................................ 16 2.5 Migrating Your BSP ............................................................................................... 17 2.6 Reference Material ................................................................................................ 20 3 Intel XScale ........................................................................................... 21 3.1 Introduction ............................................................................................................. 21 3.2 Supported Processors ............................................................................................. 22 3.3 Interface Variations ................................................................................................ 22 3.3.1 Restrictions on cret( ) and tt( ) ............................................................... 22 3.3.2 cacheLib ..................................................................................................... 23 3.3.3 dbgLib ........................................................................................................ 23 3.3.4 dbgArchLib ............................................................................................... 23 3.3.5 intALib ....................................................................................................... 24 3.3.6 intArchLib ................................................................................................. 24 iv Contents 3.3.7 vmLib ......................................................................................................... 25 3.3.8 vxALib ....................................................................................................... 25 3.3.9 vxLib ........................................................................................................... 26 3.4 Architecture Considerations ................................................................................ 26 3.4.1 Processor Mode ........................................................................................ 26 3.4.2 Byte Order ................................................................................................. 27 3.4.3 ARM and Thumb State ............................................................................ 27 3.4.4 Unaligned Accesses ................................................................................. 27 3.4.5 Interrupts and Exceptions ....................................................................... 27 Interrupt Stacks ........................................................................................ 28 Fast Interrupt (FIQ) .................................................................................. 28 3.4.6 Divide-by-Zero Handling ....................................................................... 28 3.4.7 Floating-Point Support ............................................................................ 28 3.4.8 Caches ........................................................................................................ 29 3.4.9 Memory Management Unit (MMU) ...................................................... 30 XScale Memory Management Extensions and VxWorks ................... 31 Cache and Memory Management Interaction ..................................... 38 BSP Considerations for Cache and MMU ............................................ 40 3.4.10 Memory Layout ........................................................................................ 41 3.5 Migrating Your BSP ............................................................................................... 42 3.6 Reference Material ................................................................................................ 44 4 Intel Architecture .................................................................................. 47 4.1 Introduction ............................................................................................................. 47 4.2 Supported Processors ............................................................................................ 47 4.3 Interface Variations ................................................................................................ 49 4.3.1 Supported Routines in mathALib .......................................................... 49 4.3.2 Architecture-Specific Global Variables .................................................. 49 v VxWorks Architecture Supplement, 6.2 4.3.3 Architecture-Specific Routines ..............................................................