Grand Valley State University ScholarWorks@GVSU Masters Theses Graduate Research and Creative Practice 5-19-2017 Embedded processors on FPGA: Hard-core vs Soft-core Vivek J. Vazhoth Kanhiroth Grand Valley State University Follow this and additional works at: http://scholarworks.gvsu.edu/theses Part of the Engineering Commons Recommended Citation Vazhoth Kanhiroth, Vivek J., "Embedded processors on FPGA: Hard-core vs Soft-core" (2017). Masters Theses. 845. http://scholarworks.gvsu.edu/theses/845 This Thesis is brought to you for free and open access by the Graduate Research and Creative Practice at ScholarWorks@GVSU. It has been accepted for inclusion in Masters Theses by an authorized administrator of ScholarWorks@GVSU. For more information, please contact [email protected]. Embedded processors on FPGA: Hard-core vs Soft-core Vivek Jayakrishnan Vazhoth Kanhiroth A Thesis submitted to the Graduate Faculty of GRAND VALLEY STATE UNIVERSITY In Partial Fulfilment of the Requirements For the Degree of Master of Science in Electrical Engineering Padnos College of Engineering and Computing April 2017 DEDICATION To my parents Jayakrishnan and Jayalakshmi who are my biggest inspiration and to my mentor Rajesh without whose help I would never have come out of my shell. 3 ACKNOWLEDGEMENTS I would like to thank my Thesis Advisor Dr. Chirag Parikh without whose patience, guidance and understanding I would not have finished this thesis. I would also like to thank my Thesis committee members Dr. Christian Trefftz and Dr. Azizur Rahman for their valuable inputs and feedback about my thesis. I am indebted to Dr. Shabbir Choudhuri for always being approachable and helping me on innumerable occasions over the last 3 years. In addition, I would like to thank Grand Valley State University for providing me the resources and the financial support to fulfil my dream of earning a Master’s degree in Engineering. Finally, to my friends and family without whose support I would not be where I am right now. And to the Almighty God, thank you for showing me that happiness can be found even in the darkest of times if one remembers to turn on the light. 4 ABSTRACT Field Programmable Gate Arrays (FPGAs) are integrated circuits (ICs) that can be reprogrammed by the consumer after manufacturing. They are based on a matrix of configurable logic blocks connected via programmable interconnects that enables the designer to quickly recreate hardware circuits. In the past, FPGAs were primarily used for prototyping and debugging purposes. However, with their increased popularity, many commercial products now incorporate FPGAs. In the late 1990s, FPGA vendors introduced System-on-chip (SoC) devices that housed one or more hard-core processors and an FPGA fabric on a single IC to allow for more complex designs that involved hardware and software co-integration. While this approach provides advantages of running your design at much higher speeds it does not provide the flexibility of modification to suit the application. Because of this many FPGA vendors provide the solution of using soft-core processors that are configured from logic resources inside the FPGA. While this approach provides the advantage of flexibility they run at about 30% to 50% of the speed of the hard-core processors. Thus each approach has its own advantages and disadvantages. In this thesis, an application was developed to run on two different FPGA platforms. The first platform, Digilent Zybo FPGA board, houses an ARM-Cortex hard-core while the other, Digilent Nexys-4 board, implemented ARM-Cortex soft-core using FPGA resources. IP blocks were designed in Hardware Description Languages Verilog and VHDL to interface with the processor and it’s supported Bus Architecture (AXI/AHB). The application was written in C and assembly language and enacted the function of a Digital Oscilloscope. It used the ADC ports on the FPGA board to continuously read analog signals and plotted them as a dynamic waveform on a VGA 5 monitor. Xilinx Vivado was the primary IDE used for HDL design, synthesis, simulation and implementation for both the platforms. Reports generated from Vivado as well as the run-time results were used to compare the two platforms and identify their strengths and weaknesses. Also discussed is the methodology for choosing either board over the other. 6 TABLE OF CONTENTS DEDICATION . 3 ACKNOWLEDGMENTS . 4 ABSTRACT . 5 TABLE OF CONTENTS . 7 LIST OF TABLES . 9 LIST OF FIGURES . 10 ABBREVIATIONS . 12 CHAPTER 1. INTRODUCTION 1.1 Background . .13 1.2 Field Programmable Gate Arrays . .13 1.3 Embedded processors on FPGAs . 14 1.4 Problem Statement . 15 1.5 Related Works . .15 1.6 Outline . .16 CHAPTER 2. SOFTWARE DESIGN 2.1 Overview . .17 2.2 Software flow . 18 2.3 Main functions . 19 CHAPTER 3. HARDWARE DESIGN 3.1 Platforms . .23 3.2 Bus Architecture . .27 3.3 HDL Design . 32 3.3.1 Soft-Core based design . .33 3.3.2 Hard-Core based design . 38 3.3.3 User-defined IP blocks . 42 3.3.4 Synthesis and Implementation . 47 7 CHAPTER 4. TESTING AND RESULTS 4.1 Overview . .49 4.2 Experimental setup . 49 4.3 Review of the design stages . 50 4.4 Results . .52 4.5 Observation . .56 CHAPTER 5. CONCLUSION 5.1 Summary . .58 5.2 Future Scope . .59 APPENDICES . .60 REFERENCES . .64 8 LIST OF TABLES 1. Input/output signals from Soft-core based design . 34 2. Input/output signals from Hard-core based design . .38 3. Soft-core vs Hard-core comparison . 59 9 LIST OF FIGURES 1. An overview of the contents of while loop . .17 2. Software Flowchart . .18 3. The layout of 640x480 display . .20 4. Digilent Nexys-4 board features. 24 5. Digilent Zybo board features. .26 6. Single master AHB-Lite system . .28 7. A simple AHB-Lite read transaction . 29 8. A simple AHB-Lite write transaction . .29 9. AXI-Lite Architecture . .30 10. Read transaction on AXI_Lite . 31 11. Write transaction on AXI_Lite . .32 12. Top level for the soft-core based design . .33 13. An example AMBA system . 35 14. Cortex M0 DS schematic . 36 15. System Wrapper block diagram . 37 16. Top level design for hard-core based system . 39 17. Zynq7 Processing system wrapper . 40 18. Block diagram for the Processor System Reset module . ..