<p>CH1-3: PWM lines (map to Q1,Q5,Q3 in picture below), CH4: phase current</p><p>In scope shot above: ch2 gets turned off right away, ch3 assumes new pwm settings right away, but ch1 is delayed by one pwm period. I am looking for a way to turn both ch1 and ch3 at the same time, such that there is no delay, but if there is delay I would like both of them either high or both low while waiting for change.</p><p>See our current Init and Commutation code below</p><p>//****************************************************************************** //******************* Static Non-Member Functions ****************************** //****************************************************************************** //======// // Static: PwmInit // // Description: This function was a macro in in the MotorControlpwm.h. // It sets up the PWM for the motor control. // // // Parameters: None // // // Returns: none // // Side-effects: None // static void PwmInit() { // set all pwm low EPwm1Regs.AQCSFRC.bit.CSFA = 1; // Low 1a (Ah) EPwm1Regs.AQCSFRC.bit.CSFB = 1; // Low 1b (Al) EPwm2Regs.AQCSFRC.all = EPwm1Regs.AQCSFRC.all; // Low (Bh Bl) EPwm3Regs.AQCSFRC.all = EPwm1Regs.AQCSFRC.all; // Low (Ch Cl) </p><p>// Init Timer-Base Period Register for EPWM1-EPWM3 EPwm1Regs.TBPRD = PWM_PERIOD_TICKS; EPwm2Regs.TBPRD = EPwm1Regs.TBPRD; EPwm3Regs.TBPRD = EPwm1Regs.TBPRD; </p><p>// Init Timer-Base Phase Register for EPWM1-EPWM3 EPwm1Regs.TBPHS.half.TBPHS = 0; EPwm2Regs.TBPHS.half.TBPHS = EPwm1Regs.TBPHS.half.TBPHS; EPwm3Regs.TBPHS.half.TBPHS = EPwm1Regs.TBPHS.half.TBPHS; </p><p>// Init Timer-Base Control Register for EPWM1-EPWM3 EPwm1Regs.TBCTL.bit.FREE_SOFT = SOFT_STOP_FLAG; EPwm1Regs.TBCTL.bit.PHSDIR = PHSDIR_CNT_UP; EPwm1Regs.TBCTL.bit.CLKDIV = CLKDIV_PRESCALE_X_1; EPwm1Regs.TBCTL.bit.HSPCLKDIV = HSPCLKDIV_PRESCALE_X_1; EPwm1Regs.TBCTL.bit.SYNCOSEL = 0;//TB_SYNC_IN EPwm1Regs.TBCTL.bit.PRDLD = 1;//PRDLD_IMMEDIATE; EPwm1Regs.TBCTL.bit.PHSEN = 1;//CNTLD_ENABLE; EPwm1Regs.TBCTL.bit.CTRMODE = TIMER_CNT_UP; EPwm2Regs.TBCTL.all = EPwm1Regs.TBCTL.all; EPwm3Regs.TBCTL.all = EPwm1Regs.TBCTL.all;</p><p>// Init Compare Control Register for EPWM1-EPWM3 EPwm1Regs.CMPCTL.bit.SHDWBMODE = 1; //SHDWxMODE_SHADOW; EPwm1Regs.CMPCTL.bit.SHDWAMODE = 1; //SHDWxMODE_SHADOW; EPwm1Regs.CMPCTL.bit.LOADBMODE = LOADxMODE_ZRO; EPwm1Regs.CMPCTL.bit.LOADAMODE = LOADxMODE_ZRO; EPwm2Regs.CMPCTL.all = EPwm1Regs.CMPCTL.all; EPwm3Regs.CMPCTL.all = EPwm1Regs.CMPCTL.all;</p><p>// Init Action Qualifier Output A Register for EPWM1-EPWM3 EPwm1Regs.AQCTLA.bit.CBD = AQC_NOTHING; EPwm1Regs.AQCTLA.bit.CBU = AQC_NOTHING; EPwm1Regs.AQCTLA.bit.CAD = AQC_NOTHING; EPwm1Regs.AQCTLA.bit.CAU = AQC_SET; EPwm1Regs.AQCTLA.bit.PRD = AQC_NOTHING; EPwm1Regs.AQCTLA.bit.ZRO = AQC_NOTHING; EPwm2Regs.AQCTLA.all = EPwm1Regs.AQCTLA.all; EPwm3Regs.AQCTLA.all = EPwm1Regs.AQCTLA.all; </p><p>// Init Dead-Band Generator Control Register for EPWM1-EPWM3 EPwm1Regs.DBCTL.bit.IN_MODE = 0; EPwm1Regs.DBCTL.bit.POLSEL = POLSEL_ACTIVE_HI_CMP; EPwm1Regs.DBCTL.bit.OUT_MODE = BP_ENABLE; EPwm2Regs.DBCTL.all = EPwm1Regs.DBCTL.all; EPwm3Regs.DBCTL.all = EPwm1Regs.DBCTL.all; </p><p>// Init Dead-Band Generator for EPWM1-EPWM3 EPwm1Regs.DBFED = 100; EPwm2Regs.DBFED = EPwm1Regs.DBFED; EPwm3Regs.DBFED = EPwm1Regs.DBFED; </p><p>EPwm1Regs.DBRED = 100; EPwm2Regs.DBRED = EPwm1Regs.DBRED; EPwm3Regs.DBRED = EPwm2Regs.DBRED;</p><p>// Init PWM Chopper Control Register for EPWM1-EPWM3 EPwm1Regs.PCCTL.bit.CHPDUTY = CHPDUTY_X_1; EPwm1Regs.PCCTL.bit.CHPFREQ = CHPFREQ_X_1; EPwm1Regs.PCCTL.bit.OSHTWTH = OSHTWTH_X_1; EPwm1Regs.PCCTL.bit.CHPEN = CHPEN_DISABLE; EPwm2Regs.PCCTL.all = EPwm1Regs.PCCTL.all; EPwm3Regs.PCCTL.all = EPwm1Regs.PCCTL.all; </p><p>PwmEnable = false; }</p><p>//********************************************************************* // C O M M U T A T I O N //********************************************************************* switch(CommutationState) { case COMMU_STATE_0: { // Unused EPwm3Regs.AQCSFRC.bit.CSFA = 1; // Low EPwm3Regs.AQCSFRC.bit.CSFB = 1; // Low EPwm3Regs.DBCTL.bit.OUT_MODE = BP_DISABLE; // Power In EPwm1Regs.AQCSFRC.bit.CSFA = 0; // PWM 1a (Ah) EPwm1Regs.AQCTLA.bit.CAU = 2; // high when CTR = CMPA on UP EPwm1Regs.AQCTLA.bit.PRD = 1; // low when CTR = PRD EPwm1Regs.CMPA.half.CMPA = pwm_duty_ticks; // PWM duty cycle EPwm1Regs.AQCSFRC.bit.CSFB = 0; // Comp PWM with Deadband on 1B EPwm1Regs.DBCTL.bit.OUT_MODE =BP_ENABLE;//deadband(overides CSFB) // Power Out EPwm2Regs.AQCSFRC.bit.CSFA = 0; // Shifted Complement PWM EPwm2Regs.AQCTLA.bit.CAU = 1; // Set Low CMPA on UP-count EPwm2Regs.AQCTLA.bit.CBU = 2; // Set high CPMB on UP-count EPwm2Regs.CMPA.half.CMPA = pwm_shifted_cmp_a; // PWM duty cycle EPwm2Regs.CMPB = pwm_shifted_zero; // PWM duty cycle EPwm2Regs.AQCSFRC.bit.CSFB = 0;//1; // OverRidden by DeadBand EPwm2Regs.DBCTL.bit.OUT_MODE =BP_ENABLE;//deadband(overides CSFB) </p><p> break; } </p><p>// State s2: current flows to motor windings from phase A->C, // de-energized phase = B case COMMU_STATE_1: { // Unused EPwm2Regs.AQCSFRC.bit.CSFA = 1; // Low EPwm2Regs.AQCSFRC.bit.CSFB = 1; // Low EPwm2Regs.DBCTL.bit.OUT_MODE = BP_DISABLE; // Power In EPwm1Regs.AQCSFRC.bit.CSFA = 0; // PWM 1a (Ah) EPwm1Regs.AQCTLA.bit.CAU = 2; // high when CTR = CMPA on UP EPwm1Regs.AQCTLA.bit.PRD = 1; // low when CTR = PRD EPwm1Regs.CMPA.half.CMPA = pwm_duty_ticks; // PWM duty cycle EPwm1Regs.AQCSFRC.bit.CSFB = 0; // Comp PWM with Deadband on 1B EPwm1Regs.DBCTL.bit.OUT_MODE =BP_ENABLE;//deadband(overides CSFB) </p><p>// Power Out EPwm3Regs.AQCSFRC.bit.CSFA = 0; // Shifted Complement PWM EPwm3Regs.AQCTLA.bit.CAU = 1; // Set Low CMPA on UP-count EPwm3Regs.AQCTLA.bit.CBU = 2; // Set high CPMB on UP-count EPwm3Regs.CMPA.half.CMPA = pwm_shifted_cmp_a; // PWM duty cycle EPwm3Regs.CMPB = pwm_shifted_zero; // PWM duty cycle EPwm3Regs.AQCSFRC.bit.CSFB = 0;//1; // OverRidden by DeadBand EPwm3Regs.DBCTL.bit.OUT_MODE =BP_ENABLE;//deadband(overides CSFB) break; } </p><p>// State s3: current flows to motor windings from phase B->C, // de-energized phase = A case COMMU_STATE_2: { // Unused EPwm1Regs.AQCSFRC.bit.CSFA = 1; // Low EPwm1Regs.AQCSFRC.bit.CSFB = 1; // Low EPwm1Regs.DBCTL.bit.OUT_MODE = BP_DISABLE; // Power In EPwm2Regs.AQCSFRC.bit.CSFA = 0; // PWM 2a (Bh) EPwm2Regs.AQCTLA.bit.CAU = 2; // high when CTR = CMPA on UP EPwm2Regs.AQCTLA.bit.PRD = 1; // low when CTR = PRD EPwm2Regs.CMPA.half.CMPA = pwm_duty_ticks; // PWM duty cycle EPwm2Regs.AQCSFRC.bit.CSFB = 0; // Comp PWM with Deadband on 2B EPwm2Regs.DBCTL.bit.OUT_MODE =BP_ENABLE;//deadband(overides CSFB) // Power Out EPwm3Regs.AQCSFRC.bit.CSFA = 0; // Shifted Complement PWM EPwm3Regs.AQCTLA.bit.CAU = 1; // Set Low CMPA on UP-count EPwm3Regs.AQCTLA.bit.CBU = 2; // Set high CPMB on UP-count EPwm3Regs.CMPA.half.CMPA = pwm_shifted_cmp_a; // PWM duty cycle EPwm3Regs.CMPB = pwm_shifted_zero; // PWM duty cycle EPwm3Regs.AQCSFRC.bit.CSFB = 0;//1; // OverRidden by DeadBand EPwm3Regs.DBCTL.bit.OUT_MODE =BP_ENABLE;//deadband(overides CSFB) break; } </p><p>// State s4: current flows to motor windings from phase B->A, // de-energized phase = C case COMMU_STATE_3: { // Unused EPwm3Regs.AQCSFRC.bit.CSFA = 1; // Low EPwm3Regs.AQCSFRC.bit.CSFB = 1; // Low EPwm3Regs.DBCTL.bit.OUT_MODE = BP_DISABLE; // Power In EPwm2Regs.AQCSFRC.bit.CSFA = 0; // PWM 2a (Bh) EPwm2Regs.AQCTLA.bit.CAU = 2; // high when CTR = CMPA on UP EPwm2Regs.AQCTLA.bit.PRD = 1; // low when CTR = PRD EPwm2Regs.CMPA.half.CMPA = pwm_duty_ticks; // PWM duty cycle EPwm2Regs.AQCSFRC.bit.CSFB = 0; // Comp PWM with Deadband on 2B EPwm2Regs.DBCTL.bit.OUT_MODE =BP_ENABLE;//deadband(overides CSFB) // Power Out EPwm1Regs.AQCSFRC.bit.CSFA = 0; // Shifted Complement PWM EPwm1Regs.AQCTLA.bit.CAU = 1; // Set Low CMPA on UP-count EPwm1Regs.AQCTLA.bit.CBU = 2; // Set high CPMB on UP-count EPwm1Regs.CMPA.half.CMPA = pwm_shifted_cmp_a; // PWM duty cycle EPwm1Regs.CMPB = pwm_shifted_zero; // PWM duty cycle EPwm1Regs.AQCSFRC.bit.CSFB = 0;//1; // OverRidden by DeadBand EPwm1Regs.DBCTL.bit.OUT_MODE =BP_ENABLE;//deadband(overides CSFB) </p><p> break; } </p><p>// State s5: current flows to motor windings from phase C->A, // de-energized phase = B case COMMU_STATE_4: { // Unused EPwm2Regs.AQCSFRC.bit.CSFA = 1; // Low EPwm2Regs.AQCSFRC.bit.CSFB = 1; // Low EPwm2Regs.DBCTL.bit.OUT_MODE = BP_DISABLE; // Power In EPwm3Regs.AQCSFRC.bit.CSFA = 0; // PWM 3a (Ch) EPwm3Regs.AQCTLA.bit.CAU = 2; // high when CTR = CMPA on UP EPwm3Regs.AQCTLA.bit.PRD = 1; // low when CTR = PRD EPwm3Regs.CMPA.half.CMPA = pwm_duty_ticks; // PWM duty cycle EPwm3Regs.AQCSFRC.bit.CSFB = 0; // Comp PWM with Deadband on 3B EPwm3Regs.DBCTL.bit.OUT_MODE =BP_ENABLE;//deadband(overides CSFB) // Power Out EPwm1Regs.AQCSFRC.bit.CSFA = 0; // Shifted Complement PWM EPwm1Regs.AQCTLA.bit.CAU = 1; // Low CMPA on UP-count EPwm1Regs.AQCTLA.bit.CBU = 2; // high CPMB on UP-count EPwm1Regs.CMPA.half.CMPA = pwm_shifted_cmp_a; // PWM duty cycle EPwm1Regs.CMPB = pwm_shifted_zero; // PWM duty cycle EPwm1Regs.AQCSFRC.bit.CSFB = 0;//1; // OverRidden by DeadBand EPwm1Regs.DBCTL.bit.OUT_MODE =BP_ENABLE;//deadband(overides CSFB) </p><p> break; } </p><p>// State s6: current flows to motor windings from phase C->B, // de-energized phase = A case COMMU_STATE_5: { // Unused EPwm1Regs.AQCSFRC.bit.CSFA = 1; // Low EPwm1Regs.AQCSFRC.bit.CSFB = 1; // Low EPwm1Regs.DBCTL.bit.OUT_MODE = BP_DISABLE; // Power In EPwm3Regs.AQCSFRC.bit.CSFA = 0; // PWM 3a (Ch) EPwm3Regs.AQCTLA.bit.CAU = 2; // high when CTR = CMPA on UP EPwm3Regs.AQCTLA.bit.PRD = 1; // low when CTR = PRD EPwm3Regs.CMPA.half.CMPA = pwm_duty_ticks; // PWM duty cycle EPwm3Regs.AQCSFRC.bit.CSFB = 0; // Comp PWM with Deadband on 3B EPwm3Regs.DBCTL.bit.OUT_MODE =BP_ENABLE;//deadband(overides CSFB) // Power Out EPwm2Regs.AQCSFRC.bit.CSFA = 0; // Shifted Complement PWM EPwm2Regs.AQCTLA.bit.CAU = 1; // Set Low CMPA on UP-count EPwm2Regs.AQCTLA.bit.CBU = 2; // Set high CPMB on UP-count EPwm2Regs.CMPA.half.CMPA = pwm_shifted_cmp_a; // PWM duty cycle EPwm2Regs.CMPB = pwm_shifted_zero; // PWM duty cycle EPwm2Regs.AQCSFRC.bit.CSFB = 0;//1; // OverRidden by DeadBand EPwm2Regs.DBCTL.bit.OUT_MODE =BP_ENABLE;//deadband(overides CSFB) </p><p> break; }</p><p> default: { // Ignore invalid commutation state break; } } // switch</p><p>// force pwm sync EPwm1Regs.TBCTL.bit.SWFSYNC = 1;</p>