<p>Activity 7.1A – Latches</p><p>Purpose 1. To construct and test S-R Latch circuits and test their operation 2. To construct a gated D-latch circuit and test its operation 3. To create and read the truth tables for each Latch</p><p>Equipment Computer Simulation Software 5-volt power supply IC chips: 7400, 7404, 7475 Breadboard, Logic switches LED, limiting resistor</p><p>Procedure Part 1: Background Information:</p><p>The S-R Latch is a logic device with two inputs and two outputs. The two outputs are complements of each other. If one output is HIGH (1), then the other output will be LOW (0). The outputs are assigned the names: Q and Q’</p><p>The Latch is SET when Q=1. The Latch is RESET when Q=0. The S-R in the Latches names come from the terms SET and RESET. The output of the latch depends on the condition of the inputs. </p><p>How to SET and RESET the Latch</p><p>To set the latch we have to apply a logic level to the inputs. Based on the type of inputs needed to change the state of the latch, we have two kind of latches: activeHIGH and activeLOW.</p><p>ActiveHIGH:</p><p>For an activeHIGH latch a 1 (HIGH) at the S input will set the latch (provided that the R input is 0). A 1 at the R input will reset the latch (provided that the S input is 0). ActiveLOW:</p><p>For an activeLOW latch a 0 (LOW) at the S input will set the latch (provided that the R input is 1). A 0 at the R input will reset the latch (provided that the S input is 1).</p><p>Circuits and Truth Tables:</p><p>Latches can be built with:  Two NOR gates (activeHIGH), or  Two NAND gates (activeLOW) </p><p>The logic diagram and the truth table for the activeHIGH latch is shown below:</p><p>ActiveHIGH Input Latch</p><p>Inputs Outputs S R Q Q Comments 0 0 NC NC No Change 0 1 0 1 Latch is RESET 1 0 1 0 Latch is SET 1 1 ? ? Invalid condition Truth Table for the ActiveHIGH Latch The logic diagram and the truth table for table for the active – LOW latch is shown below:</p><p>ActiveLOW Input Latch</p><p>Inputs Outputs S R Q Q Comments 0 0 ? ? Invalid Condition 0 1 1 0 Latch is SET 1 0 0 1 Latch is RESET 1 1 NC NC No change Truth Table for the ActiveLOW</p><p>Invalid Condition Notice that there are four possible input combinations, but one of them is unacceptable. This is the so-called invalid condition. If the inputs are such that they will produce the invalid condition, then the output condition of the latch is not reliable. You should not try to use the latch with this condition.</p><p>The invalid condition arises when you have input levels that will try to set and reset the latch at the same time (S = 1, R = 1 for the activeHIGH and S = 0, R = 0 for the activeLOW).</p><p>No Change Condition In both types of latches there is an input condition that will not change the condition of the latch. For example, if you have an activeHIGH latch with inputs S = 1, R = 0, then the latch is set (Q = 1). Now, if you change the S input to 0 the latch will remain set. You can toggle the S input from 0 to 1 as many times as you like and the latch will remain set (Q will not change at all). This is very important because it shows you (for the first time) a logic device that can retain the state of its output even when changes in its input conditions occur. We say that the latch can store one bit. SET and RESET Conditions These conditions were explained above. </p><p>The logic symbols for these two latches are shown below:</p><p>S Q S Q </p><p>R Q R Q </p><p>(a) Active-HIGH (b) Active-LOW Input S-R Latch Input S-R Latch Logic Symbols for SR Latches</p><p>The Gated SR Latch The gated SR latch is an SR latch with an enable input EN. If the EN input is HIGH the latch behaves exactly as the SR latch discussed previously. If the EN input is LOW (0) the gated SR latch will not change even if the inputs change. In these conditions the latch will retain its previous state.</p><p>The circuit diagram of this latch is shown below. Its truth table is the same as the truth table of the activeHIGH latch above when the EN input is HIGH.</p><p>The Gated SR Latch</p><p>The Gated D Latch Another type of latch is the gated D latch. This latch has two inputs: the D input (data) and the EN input (enable). If the latch is enabled (EN = 1) then the latch is SET (Q = 1, Q = 0) when D = 1, and it is RESET (Q = 0, Q = 1) when D = 0. In other words: if (EN = 1) Q always follows D. When the latch is disabled (EN = 0) it remains in the present condition.</p><p>The circuit diagram and truth table of this latch is shown below.</p><p>The Gated D Latch</p><p>Inputs Outputs D EN Q Q Comments 0 1 0 1 Latch is RESET 1 1 1 0 Latch is SET X 0 NC NC Latch remains in present state Truth Table for the Gated D Latch</p><p>The logic symbols for the two-gated latches are shown.</p><p>S Q D Q </p><p>EN EN </p><p>R Q Q </p><p>(a) Gated S-R Latch (b) Gated D Latch </p><p>Logic Symbols for Gated Latches Part 2: Activities:</p><p>1. ActiveHIGH SR Latch </p><p>Using the computer simulation software, build an ACTIVE-HIGH S-R Latch using 7402 discrete gates. Attach logic switches to the inputs, and a logic display to each of the outputs. Tape a copy of the circuit in the space below:</p><p>Run the simulation and complete the Truth Table for the ACTIVE-HIGH S-R Latch below:</p><p>Inputs Outputs S R Q Q 0 0 0 1 1 0 1 1 ActiveHIGH Latch Truth Table 2. Active-LOW S-R Latch Using the computer simulator software, build an ACTIVELOW SR Latch using 7400 discrete gates. Attach logic switches to the inputs, and a logic display to each of the outputs. Tape a copy of the circuit in the space below:</p><p>Run the simulation and complete the Truth Table for the ACTIVE-LOW S-R below:</p><p>Inputs Outputs S R Q Q 0 0 0 1 1 0 1 1 ActiveLOW Latch Truth Table 3. The Gated D Latch Using the computer simulation software, build the circuit for a Gated D Latch using 7408 and 7402 discrete gates. Attach logic switches to the inputs, and a logic display to each of the outputs. Tape a copy of the circuit in the space below:</p><p>Run the simulation and complete the Truth Table for the Gated D- Latch below:</p><p>Inputs Outputs D EN Q Q 0 0 0 1 1 0 1 1 Gated D Latch Truth Table 4. Gated D Latch Using the 7475 IC Repeat the last section, using an actual chip. This IC (the 7475) has four gated D latches (a quad). You will use only one of them. Observe how you should connect the pins to achieve your goal.</p><p>Breadboard the circuit shown below:</p><p>Gated D Latch Using Integrated Circuits</p><p>Open and close the appropriate switches and complete the truth table: </p><p>Inputs Outputs D EN Q Q 0 0 0 1 1 0 1 1 Truth Table of the 7475 Chip</p><p>Demonstrate the circuit to your teacher and get signature:______Conclusion 5. Breadboard the circuit for the Gated SR latch using AND, NOR and an Inverter as was shown in the background information. Connect the appropriate switches and indicators and complete the Truth Table for the circuit. </p><p>Inputs Outputs S R EN Q Q 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Gated S-R Latch Truth Table</p><p>Demonstrate the circuit to your teacher and get signature:______</p><p>6. Define each of the terms listed below:</p><p> SET</p><p> RESET</p><p> ENABLED</p><p>7. What is an INVALID condition? </p>