Engineering Circuit Analysis, Seventh Edition

Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six2.1 (p11) = 248 nm = 0.248  m (c)2.2 (p11)1 ns = 1000 ps (d)2.3 (p11)(60 W)(24 h/day)(60 min/h)(60 s/min) = 5.184 MJ; (60 W)(1 kW/1000 W)(24 h/day)(7 day/wk) (12.5 cents/kWh) = $1.26/week2.4 (p13) electrons moving left result in a positive current flowing right. Thus, I2 = + 1 mA, and I1 =  I 2 =  1 mA .2.5 (p15) v1 =  v2 so v2 =  v1 =  17 V 2.6 (p17)We have + 4.6 A flowing into the positive reference terminal of a voltage 220 mV. Using the passive sign convention, the absorbed power is Pabs = 4.6  0.220 = 1.012 W.2.7 (p17)We have a current  1.75 A flowing out of our positive voltage reference terminal, or + 1.75 A flowing into the positive reference terminal.Thus, applying the passive sign convention we find Pabs = 1.75   3.8 =  6.65 W or a generated power of  Pabs = + 6.65 W.2.8 (p17)We see that a current of + 3.2 A flows out of our positive voltage reference terminal, so a current  3.2 A flows into that positive reference terminal.Applying the passive sign convention, 100t 100t Pabs = 8e   3.2 = 25.6 e WEngineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six -100(5 10-3 )  Pabs ( t= 5 ms ) = ( - 25.6) e =  15.53 W 2.9 (p20)Moving from left to right and applying the passive sign convention,Pabs =  7  8 =  56 W Pabs = 2  8 = + 16 WPabs =  5  12 =  60 W Pabs = 8  20 = + 160 WPabs = 0.25vx  20 = [0.25   12]  20 =  60 W (Check:  56 + 16  60 + 160  60 = 0 )2.10 (p24) v -6.3 v= i R so R = = = 3.938 k  i -1.6 10-32.11 (p24) v2(- 6.3) 2 v= i R, P = v� i so P = abs abs R 21 = 1.89 W2.12 (p24)Pabs = v i P 0.24 i  abs   30 mA v  82.13 (p27)R = (4000 ft)(0.1563 /1000 ft) = 0.6252  P = i2R = (100 A)(100 A)(0.6252 ) = 6.252 kWWeight is proportional to mass, and mass is proportional to volume. Hence, new weight = old weight × new volume/old volume Since volume = cross sectional area × length and the length remains unchanged, new weight = old weight (33.6 mm2/ 21.1 mm2) = 1.59 times the old weight.Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six 3.1 (p38)5 branches 3 nodes i i Define 18-v out of the “+” terminal of the 18- V source; RA downward through resistor RA. i- i - i +13 = 0 By KCL, 18-v RA x 8-i - 3 + 13 = 0 RA i =8 + 13 - 3 = 18 A so RA 18V By Ohm’s Law, R = = 1  A 18A3.2 (p39)By KVL, + 3 + 1 + vx = 0 so vx =  4 V v By Ohm’s Law, i =x =  400 mA x 103.3 (p42)We begin by writing a simple KVL equation:-30 + 2� 8 = v10 0 where v10 has a “+” reference on the top terminal of the 10   resistor.\v10 =30 - 16 = 14 V v 14 The current down through the 10 resistor is 10 = = 1.4 A 10 10Thus, 2  1.4 = 0.6 A flows left to right through the top 2 resistor.KVL yields -v10 +2� 0.6 = vx = 0 so v x - 14 = 1.2 12.8 V3.4 (p43)A single KVL equation yields -v + R i + v + R i = 0 s11 s 2 2 vs- v s 120- 30 or i =1 2 = = 2 A R1+ R 2 30 + 15Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six P = -2� 120 abs vs1  240 W P = 22 � 30 abs R1 120 W p = 2� 30 abs vs2 60 W P = 22 � 15 abs R2 60 W(Check:  240 + 120 + 60 + 60 = 0)3.5 (p44)Writing a single KVL equation, with a clockwise current i -vx -12 + (8 + 7) i + 4 v x = 0 [1] -v and i = x [2] 30 v=24V and i = - 4 A leads to x 5 25242 1 P = � 768 mW abs 30W 5 30 4 P = + �12 1.92 W abs12 v 25 4 2 P = - �8 204.8 mW abs 8W 25 4 2 P = - �7 179.2 mW abs 7W 25 4- 4 24 P= -�4 v 创 4 =  3.072 W abs4 vx 25 x 25 5 (Check: 768 + 1920 + 204.8 + 179.2 – 3072 = 0 mW)3.6 (p46)Summing the currents entering the top node, v v 5- - 1 - + 6 = 0 10 10 leads to v = 50 V Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six 3.7 (p47)Summing the currents entering the top node, v v 5.6-x + 0.1v - x - 2 = 0 18x 9 leads to vx = 54 V v v i =x = 3 A, i= -0.1 v =  5.4 A , i =x = 6 A A 18 B x C 93.8 (p50) v v (5- 1 + 6) + + = 0 leads to v = 50 V 10 103.9 (p51) The circuit is valid as drawn. The current from each source adds, so that a total of 8 A flows through the resistor. All three elements are in parallel so each element has the same voltage across it. Since there are no voltage sources present there can be no conflict. However, if the resistor were to be removed, the resulting circuit would be in conflict with Kirchhoff’s current law (KCL).3.10 (p53)We first simplify the circuit: where Vs = 5 + 5 + 5 =15 V R = 15 + 25 +5 = 45   iV 15 \i = -s = - =  333.3 mA R 453.11 (p55) v =(5 - 1 + 6)10 //10 = 10� 5 50 V3.12 (p56)We first simplify the circuit:Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six+ where R = 4 // (2 + 2) // (10 + 10) = 4 // 4 // 20 v = 1.818 - V = 7R = 7 (1.818) = 12.73 V3.13 (p59)Noting that we can combine the two 10 resistors into a single 5 resistor, 2 v =10 = 2 V x 2+ 3 + 53.14 (p60)(1) The resistors to the right of the 125   resistor combine into R = 50 // [2 + 240 // (40 + 20)] = 25  125 By current division, i =120� 100 mA 1 125+ 25(2) The resistors to the right of the 50 resistor combine into Rx = 2 + 240 // (40 + 20) = 50 50 By current division, i= i � 50 mA 2 1 50+ 50(3) The current through the 20 resistor is 240 i � 40 mA. Thus, v3 = 20  0.04 = 0.8 V 2 240+ 40 + 20Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six 4.1 (p83) The bottom node is the obvious choice for a reference node.At the top left node v v  v  5  1  1 2 [1] 2  3 15 and at the top right node, v v  v 2  2  2 1 [2] 4 15Simplifying, we obtain-75 = 4v1  v2 [1] and 120 =  4v1 + 19v2 [2]Solving, we obtain v1 = -18.125 V and v2 = 2.5 V4.2 (p86) we number the top nodes 1, 2 and 3 moving left to right. v- v v- v At node 1, -3 =1 3 + 1 2 [1] 2 1 v- v v v- v At node 2, 0=2 1 + 2 + 2 3 [2] 1 3 4 v v- v v - v At node 3, 7=3 + 3 2 + 3 1 [3] 5 4 2Simplifying, we obtain-6 = 3v1 - 2 v 2 - v 3 [1]0= - 12v1 + 19 v 2 - 3 v 3 [2]140= - 10v1 - 5 v 2 + 19 v 3 [3]Solving, v1 = 5.235 V and v3 = 11.47 VEngineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six 4.3 (p88)There are two basic strategies here: (1) insert the quantity for A and solve; or (2) write two general equations in terms of A, then substitute and solve. Here, we’ll go with the second option. v v  v Thus, at node 1 we can write 5  1  1 2 or 3v  2v  10 [1]. 2 1 1 2 At node 2, we write v v  v A  2  2 1 or  2v  3v  2A [2]. 2 1 1 2(a) Substitute A = 2i1 into Eqn [2]. We then note that i1 = v1 – v2. So Eqn [1] is unchanged but Eqn [2] becomes 6v1  7v2  0 [2’]. Solving Eqns [1] and [2’], we find that v1 = 70/9 V.(b) Substitute A = 2v1 into Eqn [2], which then becomes 6v1  7v2  0 [2’’]. Solving Eqn [1] and Eqn [2’’] we thus obtain v1 = -10 V.4.4 (p90) Define the top left node 1, and the top right node 2.Treating these two nodes as a single supernode,4+ 9 = 3(v1 - v 2 ) + 3( v 2 - v 1 ) + 2 v 1 + 6 v 2 [1] or 13= 2v1 + 6 v 2 [1]The remaining equation is simply v1  v2 = 5 [2]Solving, v1 = 5.375 V and v2 = 375.0 mV4.5 (p91)By inspection, v1 = -3V [1] v2  v1 v2  v3 At node 2, we can write 4   or -2v1 + 3v2 – v3 = 8 [2] 1 2 v3  v2 v3  v4 At node 3, we can write 5v   . Since vx = v3 – v4, this becomes x 2 4 -2v2 - 17v3 + 19v4 = 0 [3] v4  v1 v4 v4  v3 At node 4, 0    or -6v1 - 3v3 + 13v4 = 0 [4] 2 3 4Solving, we find that v1 = -3 V (known), v 2 = -0.0270 V, v 3 = -2.081 V, and v 4 = -1.865 V.Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six 4.6 (p95) mesh 1: -6 + 14i1 + (5 + 5) i 1 - (5 + 5) i 2 = 0 [1] mesh 2: (5+ 5)i2 - (5 + 5) i 1 + 10 i 2 + 5 = 0 [2]Simplifying, 24i1- 10 i 2 = 6 [1]-10i1 + 20 i 2 = - 5 [2]Solving, i1 = 184.2 mA i2 =  157.9 mA 4.7 (p96) define clockwise i3 in third mesh. mesh 1: -10 + 4i1 - 4 i 2 + 3 = 0 [1] mesh 2: (4+ 5 + 9 + 10)i2 - 4 i 1 - 10 i 3 = 0 [2] mesh 3: -3 + (10 + 1 + 7)i3 - 10 i 2 = 0 [3]Simplifying, 4i1- 4 i 2 = 7 [1]-4i1 + 28 i 2 - 10 i 3 = 0 [2]-10i2 + 18 i 3 = 3 [3]Solving, i1 = 2.220 A and i2 = 469.9 mA4.8 (p97)(a) With A = 2i2, we can write two mesh equations: 2 = (2 + 5)i1 – 5i2 – 2i2 or 7i1 – 7i2 = 2 [1] 6 = (4+5+3)i2 – 5i1 or -5i1 + 12i2 = 6 [2] Solving, we obtain i1 = 1.347 A.(b) With A = 2vx = 2(i1 – i2)(5) = 10 i1 – 10 i2, we can write two mesh equations: 2 = (2 + 5)i1 – 5i2 – 10i1 + 10i2 or -3i1 + 5i2 = 2 [1] 6 = (4+5+3)i2 – 5i1 or -5i1 + 12i2 = 6 [2] Solving, we obtain i1 = 545.5 mA.4.9 (p99) define clockwise current i2 in top right mesh and clockwise current i3 in bottom right mesh.  form supermesh with meshes 1 and 3.Supermesh: -10 + 4i1 - 4 i 2 + (10 + 1 + 7) i 3 - 10 i 2 = 0 [1]Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six mesh 2: (4+ 5 + 9 + 10)i2 - 4 i 1 - 10 i 3 = 0 [2] remaining equation: i3- i 1 = 3 [3]Simplifying, 4i1- 14 i 2 + 18 i 3 = 10 [1]-4i1 + 28 i 2 - 10 i 3 = 0 [2] i1 + i3 = 3 [3]Solving, i1 =  1.933 A 4.10 (p100) define two clockwise currents: i2 in top right mesh, i3 in bottom right mesh. mesh 1: -80 + 10i1 + 20(i1 – i2) + 30(i1 – i3) = 0 [1] 2,3 supermesh: -30 + 40i3 + 30(i3 – i1) + 20(i2 – i1) = 0 [2] Supermesh equation: i3 – i2 = 15i1 [3]Solving, i3 = 2.604 AThus, v3 =40 ib = 104.2 VEngineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six 5.1 (p125)Shorting the 3.5-V source,骣 7+ 3 ix =2琪 = 800 mA 桫7+ 3 + 15Open circuiting the 2-A source,1 15 i ⅱ = -创3.5 = - 140 mA x 15 3+ 7 + 15ⅱ ix= i x + i x = 660 mA5.2 (p127)(1) Shorting the 3-V source, we apply nodal analysis to find: vⅱ- v v Node 1: 2 =1 2 + 1 [1] 15 7 vⅱ v- v Node 2: 4i =2 + 2 1 [2] 5 15The presence of the dependent source has introduced a new variable, requiring an additional equation: v i = 2 [3] 5Simplifying and reducing to two equations,ⅱ [4] 210= 22v1 - 7 v 2 1 1 0=v1 + 8 v 2 [5]Solving, v1=9.180 V and v2 =  1.148 V(2) Open-circuiting the 2-A source, we apply mesh analysis after defining two clockwise mesh currents i1 and i2. mesh 1: -3 + (7 + 15 + 5)i1 - 5 i 2 = 0 [1] mesh 2: i2 = -4 iⅱ [2] where iⅱ= i1 - i 2 [3]Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through SixSimplifying, 27i1- 5 i 2 = 3 [1]-4i1 + 3 i 2 = 0 [4]Solving, i1 =147.5 mA and i2 =196.7 mA so, ⅱ and ⅱ v1=7 i 1 + 3 = 1.967 V v2=5( i 1 - i 2 ) = - 245.9 mVThus, v1 = v 1  + v 1  = 11.15 V and v2 = v 2  + v 2  =  1.394 V 5.3 (p135)5 V in series with 5 k  1 mA in parallel with 5 k (arrow pointing up).-3 - 3 骣 5000 I x = (1� 10 � 1 10 ) 琪 192.3  A 桫5000+ 470005.4 (p136) 75 A in parallel with 4 M  300 V in series with 4 M (“+” on top).  40 A in parallel with 200 k  8 V in series with 200 k (“+” on right).6 M + V -1 M 4 M 0.2 MThis circuit may be further reduced to + V -300 + 8 – 3 = 10.2 M 1 M1 By voltage division, V = 305� 27.23 V 10.2+ 1* The circuit could by transformed to have a current source, but no reduction in complexity would result.Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six 5.5 (p118) 5 A in parallel with 2   10 V in series with 2  (“+” on top)  we now have 2  in series with 8   10   10 V in series with 1   1 A in parallel with 10  (arrow pointing up)  we now have 10  // 10  = 5   1 A in parallel with 5   This is the Norton equivalent5.6 (p142)(1) Removing the 2- resistor and leaving the terminals open-circuited, no current flows through the 5- resistor; hence, there is no voltage drop across it.4 So, V= V = V = 9� 2.571 V TH OC 4W 4+ 4 + 6(2) Shorting the 9-V source with the 2- resistor removed, we see5+ 4 //(4 + 6) = 7.857 W(3) We may now find I2 byVTH I2W = = 260.8 mA RTH + 25.7 (p145)(1) First, short the 3-V source and open-circuit the 7-mA source. Looking in from the terminals, we see a resistance 1 + 5 // 2 = 2.429 k  .(2) Realising that no current flows through the 1-k resistor, we quickly apply nodal analysis to find: v- 3 v -7� 10-3 + 2000 5000Solving, v =  7.857 V = V TH (“+” on top)VTH (3) ISC = =  3.235 A (source oriented with arrow pointing upwards). RTHEngineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six 5.8 (p146) Transform the dependent source to a dependent voltage source:20 k + 200V + V 1 - 1 -A simple KVL equation yields -200 V1 - 100 + V 1 = 0 or V1 =  502.5 mV = V THShorting the terminals, we then find 0-200V1 + 20000 ISC - 100 + 0 = 0 or ISC = 5 mAVTH RTH = =  100.5  ISC5.9 (p149) There are no independent sources so VTH = 0.  install a 1-V test source, “+” on top, across the open terminals. define two clockwise mesh currents iL and iR. left mesh: -20i1 + 10 iL + 30 i L - 30 i R = 0 [1] right mesh: (30+ 5)iR - 30 i L + 1 = 0 [2] and: i1 = iL - i R [3]Simplifying,-20i1 + 40 iL - 30 i R = 0 [1]-30iL + 35 i R = - 1 [2]-i1 + iL - i R = 0 [3]Solving, iR = -50 mAiR flows out of the 1-V source. The Thévenin equivalent resistance, therefore, is1 = 20  -iREngineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six5.10 (p152) First find the Thévenin equivalent connected to Rout Removing Rout, we are left with a single mesh. Define a clockwise mesh current i1.Then (2000 + 2000) i1 + 20 + 30 = 0 and i1 = 12.5 mA.-3 VTH = -40 + 30 + 2000( - 12.5� 10 ) - 35 V Shorting the sources, RTH = 2 kΩ//2 kΩ=1 kΩ1 k R out3 (a) With R=3 k W , V = - 35� 26.25 V out Rout 1+ 3(26.25)2 \ = 229.7 mW 3000(- 35/ 2)2 (b) P = = 306.3 mW max 10002 -3 (Vout ) R out (c) 20� 10= where Vout - 35 Rout1000 + R out 2 -3 35 so 20� 10 2 Rout (1000+ Rout )Solving, Rout = 16.88  or 59.23 k  Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six 5.11 (p154) convert RV3, RV4, RV5 to a T-network RT1, RT2, RT3.10 10 RT1= = 3.333 W 10+ 10 + 10 RT3= RT2 = RT1 = 3.333 W RH1 + RT1 = RS1 = 13.33   RS2 = RH2 + RT2 = 13.33   RS3 = RH3 + RT3 = 13.33  convert T-network RS1, RS2, RS3 to a - connected network RD1, RD2, RD3RS1� RS2 � RS2 RS3 RS3 RS1  RD1= RS2 = 40  RD3 = RD2 = RD1 = 40 Rin =[ (RV1// RD1) + (RV2 // RD3)] // RD2 = 11.43  Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six 6.1 (p177) Because Rule #1 states that no current flows into either input terminal, we know that the voltage on either side of resistor Rin is equal to vin.  Invoking Rule #2, which states that the voltage at both input pins must be the same, we can conclude that vout = vin6.2 (p179) R 1 v= v� v b 2R+ R 2 2 1  By Rule #2, v= v = v [1] a b 2 2 A KVL equation starting at v1 yields:-v1 + Ri 1 + Ri 1 + vout = 0 [2] (making use of Rule #1). To obtain an expression for vout in terms of the input, we need to eliminate i1.-v1 + Ri 1 + va = 0 1 v- v v- v 1 2 [3] i =1 a = 2 1 R R1 骣v- v 琪12 2  Substituting into [2], -v1 +2 R琪 + vout = 0 琪 R 桫 or vout = v 2  v 16.3 (p185)As a true design problem, there is no “unique” solution. We need to determine the total weight of the vehicle from the weight measured by four separate scales. This indicates that a summing amplifier might be practical here, since we are also told that each scale provides a voltage signal proportional to the weight measured.Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through SixR f In this type of amplifier, the output vout is given by v   v  v  v . Since we have four out R 1 2 3 wheel scales, we need to add an additional source v4 in the circuit above. If we set Rf = R, then the output voltage is the negative sum of the input voltages. Thus, if 1 mV = 1 kg at the input, 1 mV = 1 kg at the output as well. However, the negative sign will result in a negative voltage. There are several ways around the problem, but one is to add an inverting amplifier at the output with both resistors set to whatever we choose for Rf above. 6.4 (p. 188)Since the 1N750 Zener diode has a breakdown voltage of approximately 4.7 V, and we need a reference voltage of 6 V, we construct the type of circuit suggested and select Vbat = 9 V:The input voltage to the noninverting amplifier is taken to be 4.7 V (it can vary slightly depending on the current flowing through the diode). The output is simply vout = (1 + Rf/R1)(4.7). Since we want vout = 6 V, somewhat arbitrarily choosing R1 = 1 k  leads to Rf = 277  .To complete the design we need to select a value for Rref. We do this based on the current we want to flow through the Zener diode, since no current flows into the input of the op amp. Following the logic of Example 6.4 (p. 188), we design for 50% of the maximum rated diode current, or 37.5 mA, leading to Rref = (Vbat – VZener)/ IZener = (9 – 4.7)/0.0375 = 115  .6.5 (p190)We base our design on the circuit shown in Fig. 6.22 (p190). Selecting again a 9 V battery in series with a 100  resistor connected to the noninverting input terminal to the op amp, and using a 1N750 Zener diode, we expect approximately 4. 9 V at the op amp input terminals. Selecting 9.8 k  for the remaining resistor forces a current of 4.9/9.8 = 0.5 mA to flow through RL, assuming the value of RL does not somehow affect the performance of the op amp.Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through Six6.6 (p192) v out - v in + Av v d d -+ vout= Av d [1](-vd - v in) ( - v d) ( - v d - Av d ) 0 = + + [2] R1 Ri R fSimplifying [2] yields-Ri R f v in vd = Ri R f+ R1 R f +(1 + A ) R 1 R iUsing [1], we then obtain v -A R R out = i f vin R i R f+ R1 R f +(1 + A ) R 1 R i6.7 (p201)The circuit from Fig. 6.6 (p. 176) cannot be simulated without performing a more sophisticated simulation than we have discussed so far. Replacing the sinusoidal source with a 1-V dc source, however, verifies a gain of 11:Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through SixThe circuit from Fig. 6.8 (p. 177) may be simulated in a similar fashion:As a final example, we simulate the circuit in Fig. 6.9 (p. 178), which is a basic summing amplifier. Choosing all resistors to have equal value and neglecting the output resistor, we expect the output to be the negative of the sum of the three input voltages, or –(1 + 2 + 3) = –6. The simulation agrees to within 3 significant figures. The slightly nonideal behaviour of the op amp in this particular circuit is also evident in comparing the voltages at the input, which are not precisely equal, leading to the observed discrepancy with the ideal op amp prediction.6.8 (p202)Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved Engineering Circuit Analysis, Seventh Edition Practice Problem Solutions Chapters One through SixAgain, as a traditional design problem, there is no unique solution.We choose to implement our solution using a comparator circuit, with the input voltage signal connected to the noninverting input terminal, and the inverting input grounded. Selecting a –2 V source for the negative power supply ensures an output of -2 V until vsignal exceeds 0 V. Since we want an output voltage of 12 V when vsignal > 0, we select a 12 V source for the positive power supply.Engineering Circuit Analysis, 7th Edition Copyright 2007 McGraw-Hill, Inc. All Rights Reserved

Engineering Circuit Analysis, Seventh Edition

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