<p> A Novel CMOS Wideband Auto-tuning Phase Shifter Circuit </p><p>Saad M. Al-Shahrani</p><p>A novel auto-tuning phase shifter circuit suitable for integrated circuit implementation is presented. The circuit exhibits simple structure and provides phase shifting over three decades of frequency, 2kHz – 2MHz, with a minimal phase error, less than </p><p>3.5%. Simulation results using 0.5um CMOS technology and power supply ±2V are included. </p><p>Introduction: Phase shifter circuit finds wide applications in instrumentation, measurement, communication, and control systems. Literature shows different types of phase shifter which includes frequency-dependent [1], frequency-independent [2], and auto-tuning phase shifter [3-5]. The frequency-dependent phase shifter circuit provides fixed or variable phase-shift at a single frequency. On the other hand, frequency independent phase shifter provides a fixed phase shift over a wide range of frequency. Although auto-tuning phase shifter can be used as an independent- frequency phase shifter, its main application is related to phase calibration. The automatic phase shifter system presented in [3] is used to adjust the phase misalignment in the Cartesian feedback linearization circuit of a power amplifier. An auto-calibration circuit is commonly used in transceiver system to compensate gain and phase mismatching [4]. In [5] an automatic phase calibration technique based on a</p><p>PLL is reported which is used to maintain the accuracy of the quadrature signals generated. The major intention of this paper is, therefore, to present a new auto-tuning phase shifter circuit which enjoys simplicity, accuracy, and wide frequency operation.</p><p>1 Proposed Circuit: The proposed phase shifter block diagram is illustrated in Fig. 1. </p><p>The input sinusoidal signal is processed through two paths: one includes a rectifier circuit and attenuator while the second one includes 1st order allpass filter, and a rectifier circuit. To define the overlapping period between the signals, and hence the phase shift, a switch is inserted in the upper path which is controlled by the signal in the lower path. The signals at the end of both paths are subtracted and the resulting error signal e(t) is used to charge a capacitor; the generated capacitor voltage VC is used to control the filter corner frequency ωo and thus the phase shift. The negative feedback loop built in this circuit forces the error signal e(t) to go to zero which occurs when the dc voltages V1 and V3 are equal. The operation principle of the proposed structure is described in the following. Assuming ideal half wave rectifier circuits, the dc components, V1 and V3, are given by: </p><p> k V1  Ii Rx (1) </p><p>1- sin( o  90 V3  I i Rx (2) 2 where θo is the phase shift, Rx is the input resistance of the differential element, and k is the attenuation factor. By equating (1) and (2), at steady state when error signal e(t) </p><p> o 1 is zero, then o  90  sin (1 2k) (3)</p><p>From (3) phase shift θo can be controlled through the attenuation factor k which is controlled by a ratio of two resistors. This adds an advantage to this design where phase shift can be adjusted precisely independent of the process parameters variations.</p><p>Filter Circuit using MOCCII: Figure 2 shows the symbol and circuit configuration of the multi output current conveyor (MOCCII). Ideal MOCCII can be modeled as</p><p>Iz1 = Iz2 = Iz3 = Ix, Iy=0, Vx = Vy (4)</p><p>2 Voltage buffer between Y and X terminal is built using a unity negative feedback op- amp to reduce the voltage tracking error between these terminals. The filter block of </p><p>Fig. 1 is realized based on MOCCII as shown in Fig. 3. Routine analysis for the filter circuit yields the following current transfer function of the first order allpass filter </p><p>I o1 s  o (APF):  , where, ωo= 1/(RC) (5) I i s  o</p><p>From (5) the filter's corner frequency ωo can be controlled through the grounded resistor R. To add programmability feature to the filter, R is realized using two </p><p>MOSFET transistors operating in the ohmic region, see Fig. 4, which are electronically tuned through voltage VC of Fig. 1. A simple analysis shows that, with matched transistors, the nonlinearity of each transistor will be canceled by its counter part. As a result a linear programmable resistor is obtained and given by: </p><p>(V V ) 1 R  1 2  (6) I K o (Vn V p Vtn  Vtp )</p><p> where Ko and Vt are transistor's transconductance and threshold voltage respectively. </p><p>Equation (6) shows that R is linear resistor and can be controlled through biasing voltages Vn and Vp. In our case, Vp is fixed at -0.9 V while Vn is adjusted through voltage VC of Fig. 1. A simple single stage differential amplifier is used to subtract the voltage signals V1 and V3 of Fig. 1. Each half-wave rectifier circuit of Fig. 1 is realized using a single wide channel PMOS transistor biased at the edge of the triode region to avoid large voltage drop across the rectifier terminals. </p><p>Simulation Results: To confirm the validity of the proposed structure, the circuit of </p><p>Fig. 1 was simulated with HSPICE using the CMOS MOCCII given in Fig. 3b. The </p><p>CMOS transistors were modeled by the 0.5µm BSIM3V3 CMOS models made available through MOSIS. Fig. 5 shows the auto-tuning process with input signal Ii at </p><p>3 40 KHz and 0.5 attenuation factor k. As depicted in Fig. 5a the control voltage VC is adjusted through the negative feedback loop, to set the error signal e(t) to zero, and consequently R and filter phase θo are adjusted. According to equation (3) and with k </p><p> o = 0.5, phase shift θo is equal to 90 which is confirmed by simulation as shown in Fig. </p><p>5b. Table 1 shows the performance of the proposed circuit at different attenuation factors k with input signal at 40 kHz. Moreover, the proposed circuit is tested to provide fixed phase shift of 90o over wide rang of frequency, 2kHz – 2MHz. Both testes' results show good performance where phase error is less than 3.5% over wide range of phase shift and frequency. </p><p>Conclusion: In this paper, a new CMOS auto-tuning phase-shifter circuit is presented. </p><p>The circuit exhibits a simple structure and provide wide phase shifting over three decades of frequency with a minimal phase error, less than 3.5%. Simulation results using 0.5um CMOS technology and power supply ±2V are included. </p><p>Acknowledgment: The author would like to thank King Fahd University of Petroleum for supporting the work and Dr. Abuelma’atti for his valuable comments. </p><p>References</p><p>1 Chua, M., and Martin, K. : '1 GHz Programmable Analog Phase Shifter for Adaptive Antennas'. IEEE Custom Integrated circuits conf. 1998, pp. 71-714</p><p>2 Sudhakar, K., Jagadeesh, V., and Sankaran, P. : 'Precision frequency-independent variable phase phase shifter', Electronics Letters, 2nd Feb. 1995, vol. 31 no. 3, pp. 154-155</p><p>3 Dawson, J., and Lee, T. : 'Automatic Phase Alignment for a Fully Integrated Cartesian Feedback Power Amplifier System', IEEE J. of Solid-State Circuits conf., 2003, pp. 261-263</p><p>4 Yong, H., Wei, H., Shin, L., Chao, C., Wen, L., Sao, C., and David, C. : 'An auto- I/Q calibrated CMOS transceiver for 802.11g', IEEE Journal of Solid-State Circuits, November 2005, vol. 40, n 11, pp 2187-2192</p><p>4 5 Lee', D., Kim', C., and Hongl, S. : 'A Quadrature Signal Generator Using PLL Technique', 33rd European Microwave Conf., 2003, pp. 777-780</p><p>Saad Al-Shahrani (Department of Electrical Engineering, King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia). E-mail: [email protected]</p><p>5 Figure captions:</p><p>Fig. 1 The proposed phase shifter block diagram</p><p>Fig. 2 a) Block diagram of the multi output current conveyor symbol b) Multi output current conveyor circuit configuration</p><p>Fig. 3 Current-mode first-order All-pass filter.</p><p>Fig. 4 Linear programmable resistor</p><p>Fig. 5 a) The control voltage VC over the tuning period. b) Input and output signals after tuning.</p><p>Table 1: Phase of the output signal IO , at frequency= 40kHz.</p><p>6 Figure 1</p><p>Figure 2 I =I |θ V AP Filter AP i o Half Wave 2 1st order Rectifier I =I I |0 o A V i 3 P _ k V + Half Wave 1 e(t) + Rectifier + C V C -</p><p>I I Z Z1 X X 1 I CCII Z Z2 V 2 Y Y Z I 3 Z3</p><p>(a)</p><p>1. 75V Figure 4 V n</p><p>1. 50V I</p><p>V R V 1. 25V 1 2</p><p>1. 00V 0s 5ms 10ms V 15ms Time p VV( Vr ) C (a)Ti me </p><p>500mV 10 uAFigure 5 (b) Figure 3</p><p>0V0A</p><p>R Z X 1 CCII Z -10 uA Z 2 -500mV 1 Y (2) 14. 90ms 14. 92msX 14. 94msZ 14. 96ms 14. 98ms 15. 00msZ CCII 2 3 I. 95*V( Vap) IV( V26: +) Time C Io Yi (1) Z Ti me i 3(b)</p><p>I o1 I =-I o2 o1</p><p> k Io2-Phase (cal.) Io2-Phase (simul.) Error % 0.12 40o 39.9o -0.10 Table 1 0.25 60o 60.6o 1.03 0.50 90o 89.0o -1.1 7 0.75 120o 117.6o -2.00 0.88 139.4o 136.8o -2.0 0.99 166o 164.9o -1</p>